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EDA360 – System Realization Webinar: FPGA-based prototyping is hard to do – or is it?

 
Type:
Webinar  
Orignal webinar date:
14 Sep 2011 (3pm (GMT) 4pm (CET))  
Location:
Online  
  View Webinar »  

Almost every digital SoC, ASIC and ASSP is prototyped in FPGAs; sometimes as a high-performance verification platform, but most often to get a head-start in developing software for the SoC. No matter what the purpose though, it is difficult to do and it takes too much time and too much effort, to get the prototype up and running. But does it really have to be so hard?

In this seminar we will discuss how state-of-the art FPGA devices, combined with an innovative implementation methodology can change the way we do FPGA-based prototyping, making it easier to use, easier to deploy and much, much faster to get the prototype up and running.

Topics to be covered:
  • The big picture: what is prototyping good for and what it’s not good for
  • It is hard: common challenges and issues
  • Making life easier: choosing the right tool for the job
  • The icing on the cake: tips and tricks on how to get the most out of your FPGA-based prototype
Who should attend?
  • Verification engineers
  • System integrators
  • ASIC designers
  • Embedded software, firmware, diver, operating system developers

Questions About this Event?
Send email to webinar_info@cadence.com

View Webinar »