Home > About Cadence > Events > Event Details

System-Level Simulation Acceleration with UVM/OVM

 
Type:
Webinar  
Orignal webinar date:
01 Dec 2010  
Location:
Available On-Demand  
  View Webinar »  

The Universal/Open Verification Methodologies have greatly streamlined the RTL verification process for SoCs. But at the same time, the amount of software necessary to integrate the SoC into a working device has exploded, making the software integration and debug problem the new bottleneck in delivering a working system. Software developers need a pre-silicon simulation platform that is accurate enough to reflect the subtleties of the SoC design’s RTL, yet fast enough to execute meaningful code paths. The answer, we will argue in this Webinar, is hardware simulation acceleration integrated into a solid UVM/OVM verification environment. We will describe at length how to achieve this integration.

Who should attend?
  • OVM/UVM simulation users
  • System Engineers & Managers
  • SystemVerilog or e users
  • Hardware assisted verification users
  • Verification managers & engineers

Presenter
Raj Mathur, Senior Product Management, Cadence Design Systems, Inc.
Raj Mathur serves as Sr. Product Marketing Manager in Cadence’s SD&V Product Management team. Raj drives a pivotal role in product marketing for metric driven verification for acceleration; transaction based acceleration, and accelerated VIP for current and next generation HW-assisted verification products/solutions. Raj has 20 years of engineering and marketing experience spanning products and technologies from DSP, rapid prototyping, FPGA, and hardware accelerator. Prior to joining Cadence, Raj led the marketing team at Liga Systems and led management roles at Altera and Aptix. Raj also held leading engineering positions at Aptix, Stanford Research Systems and Analog Devices.

Phu Huynh, Verification Architect, Cadence Design Systems, Inc.
Phu Huynh has over 20 years of experience in ASIC design & verification in networking and processor applications. Phu is currently a verification architect in the Cadence Verification Division. Before joining Cadence, Phu was the CTO and co-founder of SanBar Networks, a startup developing a 10 Gbps IP storage processor for SAN applications. Prior to SanBar Networks, Phu was the director of engineering at the Tality Datacom/Telecom design center in Santa Barbara. Phu has also worked at Cisco Systems, Hughes Electronics, and Delco Electronics in various management and technical positions in ASIC, software, and system design. Phu has a BSEE and an MSEE from the University of California, Santa Barbara.

Questions About this Event?
Send email to webinar_info@cadence.com


View Webinar »