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How to achieve system level functional coverage closure faster

 
Type:
Webinar  
Orignal webinar date:
21 Apr 2011  
Location:
Available On-Demand  
  View Webinar »  

With more and more software content in chips—embedded or application level—RTL design and verification is no longer the main bottleneck to a faster tapeout schedule. System integration, including embedded software development and verification are rapidly becoming the key areas to focus on with regard to cost and product delivery schedules. Defining and implementing verification intelligence at the system level is paramount to achieving RTL closure. This webinar provides design and verification engineers insights into advanced methods applied to achieve RTL closure. It delivers insights into accelerating UVM-based system level simulations with requisite functional coverage metrics. Attendees will get an overview of how to apply leading edge high-performing UVM-based solutions using hardware acceleration and standard verification methodologies to conduct hardware/software co-verification, and shorten system-level design and verification cycles.

Who should attend?
  • OVM/UVM simulation users
  • System Engineers & Managers
  • SystemVerilog or e users
  • Hardware assisted verification users
  • Verification managers & engineers

What you will learn
  • Principles of Metric Driven Verification with hardware acceleration
  • How to apply functional coverage with acceleration
  • Learn about the Cadence Kit to jump-start acceleration efforts

Presenter
Raj Mathur
Senior Product Management, Cadence Design Systems, Inc.

Raj Mathur serves as Sr. Product Marketing Manager in Cadence's SD&V Product Management team. Raj drives a pivotal role in product marketing for metric driven verification for acceleration, transaction based acceleration, and accelerated VIP for current and next generation HW-assisted verification products/solutions. Raj has 20 years of engineering and marketing experience with products and technologies from DSP, rapid prototyping, FPGA, and hardware accelerator. Prior to joining Cadence, Raj led the marketing team at Liga Systems and led management roles at Altera and Aptix. Raj also held leading engineering positions at Aptix, Stanford Research Systems and Analog Devices.

Eric Melancon
Senior Product Engineer, Cadence Design Systems, Inc.

Eric Melancon serves as a Sr. Product Engineer in Cadence's System Realization group. Eric is focused on introducing new technology optimizing the use of HW-assisted verification products. Eric has 28 years of experience in all aspects of digital verification. Eric joined Cadence through the acquisition of Quickturn Design Systems. Previously, Eric held engineering and management positions at Zycad and Mentor Graphics. Eric started his career as an IC designer at Sandia National Labs.

Questions About this Event?
Send email to webinar_info@cadence.com


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