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ARM Technology Conference 2011

 
Type:
Conference & Exhibition  
Date:
25 Oct 2011 - 27 Oct 2011  
Location:
Santa Clara, CA  

Cadence is the official signature sponsor of this year’s ARM TechCon. Don’t miss our industry address, the fireside chat, our paper and session presentations, and our exhibit in Booths 29 and 500.

Cadence and ARM have collaborated successfully for decades on the design and verification of high-performance ARM core-based designs. We offer an optimized solution that includes a full set of interoperable tools with ARM processor and physical IP; services; a system-to-silicon methodology; and a full suite of chip/package/board co-design capabilities.

At this year’s event, you’ll find out how the Cadence-ARM partnership is enabling customers to build revolutionary electronics products with verified, reusable hardware and software IP blocks—faster and with greater confidence that their systems will be manufacturable on first pass.

What you will see

Day 1: Chip Design Conference – October 25
  • Cadence Industry Address (9:30am – 10:15am)
    • Chi-Ping Hsu – Sr. Vice President, Research and Development, Cadence
    • Innovative collaboration for Silicon Realization Challenges
      Find out how Cadence and ARM are collaborating to bring your cutting-edge, advanced-node designs to market more efficiently. Together with leading foundry partners, Cadence and ARM can help you design, implement, and verify your high-speed/high-performance ARM-based SoCs at the most advanced process nodes. Learn more about our collaborative ecosystem that's committed to accelerating your success with complex designs at 32, 28, and 20nm. This industry address is a must see if you're a chip designer looking to navigate tomorrow's design challenges and take SoC innovation to the next level, today.
  • Cadence and ARM Fireside Chat (5:00pm – 6:00pm)
    • Lip-Bu Tan, Chief Executive Officer, Cadence
    • Simon Segars, EVP and GM, Physical IP Division, ARM
    • Post Reception Sponsored by Cadence (6:00pm – 7:00pm), Expo Hall
  • Cadence Booth #29
    • Cadence Design IP for Memory
      Cadence Design IP for Memory, formerly Databahn from Denali Software, supports a broad range of the latest in memory standards and technologies. In this demo, you will learn about how Cadence Design IP allows customers to integrate DDR4 and Wide IO developments into their designs for high performance and low power

    • Successful Silicon Realization of Low-Power and GHz+ ARM Cortex Application Processor-Based SoCs
      Are you planning on designing a next-generation ARM® Cortex™-A9 or Cortex-A15 MPCore™-based SoC for a consumer, networking, enterprise, or mobile end product (smartbook, large-screen mobile device, high-end wireless and smartphone platform, handheld and console gaming device, low-power server)? Does your SoC also embed leading-edge GPUs such as the Mali™ 400 or T604?

      Visit Cadence in Booth 29 to learn how a leading-edge and optimized ARM implementation reference methodology (iRM) for ARM IP can help you get a head start on achieving industry-leading power, performance, and area (PPA) targets. You will walk away with an excellent understanding of how the comprehensive and production-proven Cadence® Encounter® unified digital flow can enhance your competitive advantage by improving productivity and time-to-market goals.

    • Using Clock Concurrent Optimization to Boost Performance and Reduce Power for Your ARM Cortex-A9-Based Design
      ARM Cortex-A9 dual-core processor-based SoCs are becoming commonplace in today’s ingenious handheld devices, such as smartphones and tablets. Nevertheless, as SoC implementers move to newer process nodes (32, 28, 20nm) and push the performance envelope, timing closure becomes a nightmare. To a significant extent, this can be traced to the traditional way of building clock trees with ideal clocks. The combination of on-chip variation, gated clocks, and sheer design/clock complexity only exacerbate this problem.

      Visit Cadence in Booth 29 to learn about an automated technology―clock concurrent optimization―in the Cadence Encounter unified digital flow. It uses a timing window-based CTS concurrently with logic sizing and timing-driven placement, delivering superior timing results. This new approach to timing closure helps increase the clock frequency by up to 10% for a multi-GHz design and reduce clock-tree power and area up to 30%.
  • Sponsored Session – Tuesday 2:00 pm, room C
    • Unified Flow for Mixed-Signal Design with an Embedded Cortex-M0
      Speakers:
      - Mladen Nizic, Engineering Director, Cadence
      - Dominic Pajak, Embedded Segment Manager, ARM
      - Raviraj Mahatme, Platform Marketing Manager , ARM

      Cortex-M0 processors are often integrated with analog/mixed-signal IP including data converters, interfaces, RF-ICs, sensors, and memory blocks. Designers must verify functionality for all modes of operation, optimize the floorplan, implement core and IP blocks, signoff on performance specs for timing, noise, and power, and effectively manage analog and/or digital ECOs.

      In this presentation, you will learn how to overcome these challenges by using a mixed-signal flow that integrates advanced analog and digital design capabilities and leverages the OpenAccess database. The flow supports a unified methodology that captures, communicates, and verifies design intent; abstracts AMS designs for scalability; and, ensures continuous design convergence.
  • Technical Papers
Days 2 and 3: System and Software Design Conference – October 26 and 27
  • Cadence Booth #500
    • System Development Suite: Featuring the Rapid Prototyping Platform
      In this demo, you will learn how the Cadence Rapid Prototyping Platform, a complete FPGA-based prototyping solution, enables early, pre-silicon software development and system validation for ARM-based designs.
    • Verification IP Catalog: ACE and AMBA 4 Verification Solution
      Cadence provides the leading ACE verification solution including Verification IP (VIP) and the Interconnect Monitor (ICM). See the depth of the offering and find out how Cadence VIP and the ICM work together to ensure your ACE-based SoC is fully coherent and compliant with the ACE specification. Learn more about how Cadence works closely with ARM to ensure a single representation of the AMBA 4 specifications.
    • System Development Suite Featuring the Virtual System Platform
      This demo shows a high-performance, quad-core Cortex-A15 running SMP Linux in a virtual prototype using the Cadence Virtual System Platform. Witness the Virtual System Platform's SystemC creation and debugging capabilities, along with the export of the runtime software development virtual prototype.
  • ARM Booth #300
    • Cadence Virtual System Platform
      The new Virtual System Platform, part of the Cadence System Development Suite, can help you begin software development months ahead of RTL completion and prevent slips in RTL and FPGA prototype schedules. The demonstration includes a virtual prototype using ARM Fast Models, running at-speed, simulating an Android-based smartphone accessing web pages on the Internet. The demo will also show the Virtual System Platform's integrated hardware/software multi-core debugging and SystemC code generation capabilities. The Virtual System Platform utilizes cycle-accurate SystemC or RTL for portions of the design to support detailed analysis of the system architecture, simulating the RTL with the integrated Incisive Verification Platform or using the Palladium XP Verification Computing Platform to emulate the RTL at higher speeds.
  • Sponsored Session – Wednesday 3:30pm, room H
    • Verifying Your ACE-Based SoC: Will Tried and True Methods Hold Up?
      Speaker:
      - Mirit Fromovich, Verification IP Solutions Architect, Cadence
      - Paul Martin, Design Enablement and Alliances Manager, ARM

      Verifying cache-coherent SoCs/systems employing ARM’s new AMBA® 4 ACE™ protocol is challenging since only up-to-date data may be used. It’s not sufficient for engineers to simply read the ACE specification―they need specialized verification tools for ACE-based designs. But not just any verification IP (VIP) will do. Verifying ACE coherency is well beyond the ability of directed testing, the basic scheme most designers employ. Directed testing is insufficient to cover the range of scenarios and checks needed to validate coherency. Verifying system-level coherence requires two key capabilities: (1) constrained random stimulus generation capability; and (2) an interconnect monitoring solution.

      In this presentation, you will learn about the full range of cache-coherency issues faced when verifying an SoC; how to define a verification strategy; how to create testing scenarios to deliver high-quality end products; and, what to look for when selecting an ACE verification solution.
  • Technical Paper
Who should attend?
  • Engineers, engineering managers, executives, and individuals using ARM processors

Questions About this Event?
Send email to events@cadence.com