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Archived webinar - Moving Design and Verification to the Next Level with High-Level Synthesis

Original webinar date:
07 Sep 2011  
Online, 3pm (GMT) 4pm (CET)  
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Designing and verifying at the transaction-level of abstraction has promised great productivity and time-savings benefits, but until recently this has been limited to datapath blocks. But recent breakthroughs in synthesis algorithms and growing understanding of how to use SystemC to express a wider variety of structures are dissolving that limitation.

In this webinar we will describe and illustrate how to create SystemC code for synthesis, how to extend your verification environment to this level, how to analyze your high-level design, drive the new SystemC-to-RTL synthesis tools, and take the measures that will ensure the kind of netlist you want down-stream. It’s not just for datapath anymore.
    Who should attend?
  • Verification engineers
  • System integrators
  • ASIC designers
  • Embedded software, firmware, diver, operating system developers

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