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Archived webinar - Quickly Find Data Transport Bugs with Formal Scoreboarding

Original webinar date:
17 Nov 2011 9:00 AM  
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“Scoreboards” have been used in advanced simulation testbench environments for years. In this webinar, we will show how this same concept can be implemented with formal verification tools. Consequently, you will see how to benefit from powerful formal analysis algorithms to automatically test data integrity and root out the spectrum of simple problems to extreme corner cases.

The formal scoreboarding methodology is flexible and extendable such that it can be applied to various data transport blocks including bridges, switches, routers, matrices, memory controllers, DMA controllers, and buffers. Its value to the user is a significant reduction in simulator runtime and the ability to find bugs faster with less effort. This is an exciting topic for anyone in the functional verification space. A demonstration will reinforce the concepts learned during the session.

Who should attend?
  • Verification engineers, verification leads, designers, and managers interested in improving quality, productivity, and predictability of their verification process
  • Recommended background: hardware simulation experience only

What you will learn
  • Understanding and using scoreboards
  • How to apply the flow in your verification environment presentation
  • Scoreboarding examples with popular protocols

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