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Archived webinar: Automate Assertion Generation for Simulation, Formal and Emulation Flows

Original webinar date:
13 Oct 2011  
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Assertion-based verification (ABV) helps design and verification teams using simulation, formal analysis, and emulation methodologies accelerate verification signoff by enhancing the RTL and test specifications to include assertions and functional coverage properties, which are logic statements that define the intended behavior of signals in the design.

The emergence of “assertion synthesis” will allow for true proliferation of ABV by automating the painful manual process of creating meaningful white-box assertions and functional coverage properties with sufficient capacity to handle complex SoC designs. Without writing any additional code, stimulus generation and running additional tests will find additional bugs and improve functional coverage, integrating into your metric-driven verification (MDV) flow.

In this webinar, Cadence and NextOp Software will show how assertion synthesis enables a progressive, targeted verification process, allowing design and verification teams to more easily uncover corner-case bugs, expose functional coverage holes, and increase verification observability. A demonstration will reinforce the concepts learned during the session.

Who should attend?
  • Verification engineers who are implementing testbenches
  • Verification/project managers responsible for technology and implementations
  • Project leaders using simulation, formal, and emulation techniques
  • Recommended background: a solid understanding of assertion-based verification

What you will learn
  • Introduction to assertion-based verification and analysis
  • Introduction to assertion synthesis for white-box testing
  • Technology overview / integrating Cadence and NextOp tools
  • Tips and tricks to optimize coverage in your metric-driven verification flow

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