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Archived webinar - Applying Digital Verification Methodologies to Analog Design

 
Type:
Webinar  
Orignal webinar date:
15 Sep 2011  
Location:
Online  
  View Webinar »  

Traditionally, analog blocks are already verified at the block level, but at the SoC level, many things still go wrong with connectivity and control of the analog circuit. Integration of analog blocks into digital simulations is not enough, and we need to apply the concepts of an advanced digital verification methodology to the analog domain in order to achieve the same productivity. At the heart of the problem is knowing what’s going wrong with the analog models in the discrete digital domain and gaining insight into key verification metrics for signoff.

This webinar will discuss how to approach analog block integration regardless of abstraction level (Spice, AMS models, real number models) and how to increase your verification quality and productivity using a metric-driven approach. Presented by expert user Dan Romaine, the goal of this webinar is to share:
  • How to plan for and link to coverage of analog blocks with an executable verification plan
  • Understanding how analog-specific assertions can be add to your overall metrics
  • How a digital/mixed-signal model enables advanced metric-driven verification
Who should attend?
  • Verification engineers, verification leads, designers, and managers interested in improving quality, productivity, and predictability of their verification process
  • quality, productivity, and predictability of their verification process Recommended background: SoC integration level
  • Solid understanding of metric-driven or coverage-driven verification

What you will learn
  • Verification coverage philosophy and implementation guidelines
  • Guidelines for augmenting traditional analog verification when integrating at the SoC level
  • Understanding how adding these types of metrics help you reduce your potential risk
  • Anatomy of analog-centric coverage metrics and what information should be provided
  • Guidelines for building assertions that measure voltage and current

Questions About this Event?
Send email to webinar_info@cadence.com

View Webinar »