To address their verification challenges, customers have been using many different verification languages like Verilog, VHDL, e, SystemVerilog, and SystemC. As customers have become more sophisticated and sought to exchange and reuse verification IP, they have coalesced on two IEEE standardized verification languages – 1800 SystemVerilog and 1647 e – which both have broad industry support. And while customers have been successfully using e as their verification language for more than 10 years, SystemVerilog is emerging as the one-size-fits-all language for verification.
Methodology is the biggest advantage verification engineers have to cut through the noise and put language features and, hence, productivity into context. With the advent of the Universal Verification Methodology’s (UVM’s) support of e and SystemVerilog, languages are now set within a common methodology framework, with feature comparisons such as coding efficiency, AOP vs. OOP, design patterns, randomization vs. generation schemes—tool support becomes apparent and compelling. With HVL standardization, the importance of consistent, open, and interoperable methodologies are more evident than ever, and verification engineers can finally freely choose. Just like choosing Apples or PCs, understanding the pros and cons of both languages will end your debate of which language to choose. This webinar will also technically compare and contrast UVM e and UVM SystemVerilog to assist you in choosing which language would best meet your verification needs.
Who should attend?
- Verification engineers, verification leads, designers, and managers interested in improving quality, productivity, and predictability of their verification process
- Verification engineers interested in learning more about the differences between e and SystemVerilog languages
What you will learn
- Brief history of SystemVerilog and e evolution
- Apples-to-apples comparison between HVLs for common verification challenges
- Pros and cons of aspect-oriented programming (AOP) in e vs. object-oriented programming (OOP) in SystemVerilog
- e generation vs. SystemVerilog randomization
- Cadence recommendation for HVL verification
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