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Archived webinar - Finding the Bugs in Your UVM Haystack

 
Type:
Webinar  
Orignal webinar date:
23 Aug 2011  
Location:
Online  
  View Webinar »  

Bugs are hard enough to find in a complex design, but when you add in the Universal Verification Methodology (UVM) the haystack becomes huge. Is the bug in your design or in the testbench? If you see an error reported by UVM, when did the bug actually occur? Due to complexity, bugs often appear as errors dozens or hundreds of cycles separated from their actual occurrence. With these challenges, verification engineers need a sophisticated tool belt to find the bugs in the haystack of data produced by the simulator. SimVision provides just that.

Since UVM defines class-based, transaction-driven test benches, you need a debug environment centered on these elements. SimVision enables you to access the environment through both the class inheritance and the instance trees. Within the source code, you can bring any of the SystemVerilog datatypes in the waveform viewer and you can set breakpoint in several ways. You can follow the simulation flow single stepping through/over lines, method calls, and even into macros. UVM provides automatic transaction recording so that you can view your test sequences and SimVision adds a novel stripe chart view that allows you to visualize the sequential order of transactions across multiple streams. While you will probably be thrilled to use all of these capabilities interactively, it’s just not possible to do across the thousands of regressions you run. SimVision and the Incisive Enterprise Simulator also provide both save/restore and post-processing capabilities. Our debug architect Mike Floyd has assisted multiple users with the following tasks:
  • Visualizing the entire UVM class structure with the ability to hide the UVM BCL as needed
  • Setting break points and step through any code including macros
  • Adding any SystemVerilog datatypes to the waveform viewer
  • Visualizing and connect transactions in the waveform, stripe chart, and source code
  • Efficiently managing simulation and debug time using save/restore and post-processing
This webinar will help you see how GUI-based debug can improve your productivity over embedded print statements enabling you to visualize your UVM class structure, data, transactions, and more. It will focus on the debug capabilities in SimVision that will help you find those bugs no matter where they are in the haystack of data.

Who should attend?
  • Verification engineers, verification leads, designers, and managers building UVM environments
  • Recommended background: Solid understanding of the UVM methodology is a prerequisite

What you will learn
  • Differences between debugging static design code and dynamic testbench code
  • How to interact with methods and data that are created and destroyed during the execution of a test
  • Methods for identifying bugs separated from the UVM error messages by multiple cycles using transactions and stripe charts
  • Approaches for managing simulation performance during debug sessions using save/restart
  • Post-processing methods to debug regression simulations

Questions About this Event?
Send email to webinar_info@cadence.com

View Webinar »