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Archived webinar - Cadence and IC Manage - IP Reuse and Parasitic-Aware Design Using Cadence Virtuoso Technologies and the IC Manage Global Design Platform

 
Type:
Webinar  
Orignal webinar date:
28 Jun 2011  
Location:
Online  
  View Webinar »  

Technology experts from IC Manage and Cadence present the advancements in the area of custom IC design and verification, focusing on IP collaboration/reuse and parasitic-aware design.

See a live demonstration of a methodology that global design and verification teams can use to deploy the Cadence Virtuoso-based unified custom/analog flow and the IC Manage Global Design Platform (GDP) to access, integrate, verify, and track IP dynamically throughout the SoC/IC design process, across various data sources.

The parasitic-aware design flow is a methodology that Cadence Virtuoso unified custom/analog flow users can leverage to better assess the impact of physical implementation on the overall specifications for the design. Users can specify IP, reuse IP, or create new estimations for parasitics in their designs through a combination of engineering know-how, Virtuoso design capabilities, and in-design signoff verification to identify trouble areas before they become troublesome. By combining design constraints, measurements, rapid analog prototyping, and signoff-quality verification into a cohesive and connected design flow, a parasitic-aware design flow ensures that you’ll never again be left with a “what now!?” just before a tapeout.


Who should attend?
  • Custom/analog engineers, engineering management

What you will learn
  • Importing IP or PDKs into the IC Manage GDP
  • Using the IC Manage Project Manager to automatically generate workspaces for the Cadence Virtuoso unified custom/analog flow
  • Using the IC Manage Library Browser within the Cadence Virtuoso custom/analog flow for high-performance data management
  • Using the IC Manage differencing utilities for schematics, layout, and GDSII
  • Managing the release process for IP or designs
  • Assembling IP and designs for chip-level integration in the Cadence Virtuoso unified custom/analog flow
  • Creating and managing derivative designs for experiments, re-spins, and new functionality
  • Using the IC Manage GDP inside the Cadence Virtuoso unified custom/analog flow to integrate bug tracking

Questions About this Event?
Send email to webinar_info@cadence.com

View Webinar »