With the increase in standards-based interfaces on high pin-count FPGAs, the time to integrate FPGAs on printed circuit boards is growing significantly.
PCB-optimized FPGA pin assignments that don’t add layers to a board or increase design-in time is a challenge for the entire design team. FPGA designers, hardware designers, and PCB designers struggle to create FPGA pin assignments that meet the goals for the entire system. In this one-hour webinar, you will see how Cadence Allegro FPGA System Planner and Allegro PCB Editor can be used seamlessly with Altera’s Quartus II FPGA design tools to shorten time to design-in large pin-count FPGAs and optimize PCB layout.
Who should attend?
- FPGA designers
- Hardware designers
- Hardware design managers
Relevant tools and software:
- Altera Quartus II software
- Allegro FPGA System Planner
- Allegro Design Entry HDL
- Allegro PCB Design HDL
What you will learn
- Capture timing-critical pin assignments using Altera Quartus II software
- Use Allegro FPGA System Planner to refine Quartus II pin assignments to better meet system-level design goals
- Generate first-cut FPGA I/O DRC-aware and route-aware pin assignments for rest of the signals using Allegro FPGA System Planner
- Generate required PCB files from the Allegro FPGA System Planner design
- Optimize pin assignments for routing using FPGA System Planner and Allegro PCB Editor
Questions About this Event?Send email to firstname.lastname@example.org