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Archived webinar - Accelerating Design-in of Xilinx FPGAs while Optimizing PCB Layout for Cost and Performance

Original webinar date:
15 Jun 2011  
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The time to integrate FPGAs on printed circuit boards is growing significantly because of the increase in standards-based interfaces on high pin-count FPGAs. Additionally, design teams do not want to add layers to a board nor increase design-in time.

FPGA designers, hardware designers, and PCB designers struggle to create FPGA pin assignments that meet the goals for the entire system. In this one-hour webinar, you will see how Cadence Allegro FPGA System Planner and Allegro PCB Editor can be used seamlessly with the Xilinx PlanAhead design tool to shorten time to design-in large pin-count FPGAs and reduce PCB layer count.

Who should attend?
  • FPGA designers
  • Hardware designers
  • Hardware design managers
Relevant tools and software:
  • Xilinx PlanAhead software
  • Allegro FPGA System Planner
  • Allegro Design Entry HDL
  • Allegro PCB Design HDL

What you will learn
  • Use Xilinx PlanAhead design tool to complete an initial FPGA pin-out on a design containing an external memory interface
  • Use Allegro FPGA System Planner to refine the FPGA pin assignments to better meet system-level design goals
  • Generate board routing and FPGA logic/timing-aware pin assignments for the rest of the signals using Allegro FPGA System Planner
  • Optimize pins from the Xilinx PlanAhead tool and IP library for a PCB without affecting the IP logic or IP timing requirements
  • Generate required PCB files from the Allegro FPGA System Planner design
  • Optimize FPGA pin assignments after PCB layout using Allegro FPGA System Planner

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