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Archived webinar - How to Completely Eliminate SoC Connectivity Bugs - Really!

 
Type:
Webinar  
Orignal webinar date:
24 Mar 2011  
Location:
Online  
  View Webinar »  

Bugs from incorrect connectivity—whether they’re misconnected IP blocks inside an SoC or erroneous muxing of pad rings—can kill a chip just easily as more sophisticated functional bugs. With internal connection points surpassing hundreds of thousands of nodes, the traditional approach of assigning detail-oriented summer interns to spot-check connectivity with some dynamic simulations is rapidly losing effectiveness. How do you ensure that two versions of your design are equivalent (e.g., the design before power techniques and after)?

In this technical webinar, we’ll show you how to apply formal verification technology to exhaustively prove with 100% mathematical certainty that all of your SoC’s internal and external pad ring connections are completely correct. A demonstration will reinforce the concepts learned during the session.


Questions About this Event?
Send email to webinar_info@cadence.com

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