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Archived webinar - Building Automated and Reusable Testbenches Using the SystemVerilog UVM

Orignal webinar date:
17 Mar 2011  
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This technical session targets users who are new to SystemVerilog to learn the basics of building testbenches using the SystemVerilog language and the Universal Verification Methodology (UVM). We will review the history of the UVM and what it provides to create a powerful testbench with automated stimulus, checking, and functional coverage capabilities. This webinar will also introduce powerful debug and coverage analysis capabilities. Finally, we will introduce different resources that users can utilize to learn more about the UVM at their own pace. A demonstration will reinforce the concepts learned during the session.

Questions About this Event?
Send email to webinar_info@cadence.com

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