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EDA360 Tech on Tour: Silicon Realization / Mixed-Signal R&D

 
Type:
Seminar  
Date:
24 Feb 2011 - 24 Feb 2011  
Location:
Austin, TX - February 23
Irvine, CA - February 24
 

Virtually all modern IC and SoC designs are mixed signal. Most systems have to interface their millions of gates, DSPs, memories, and processors to the real world through one or more analog or mixed-signal subsystems such as a display, an antenna, a sensor, a cable, or an RF interface. Successfully taping out a mixed-signal design on schedule with the lowest power consumption and within budget is becoming more and more challenging as the mixed-signal designs become bigger and more complex.

In this full-day technical seminar, you’ll learn best practices and gain valuable insights from Cadence mixed-signal R&D experts on how to realize today’s highly integrated and complex mixed-signal designs more productively and profitably. You’ll also hear case studies of how design teams are successfully using Cadence mixed-signal solutions to achieve their tape-out goals, optimize performance and power, reduce costs, improve turnaround time and mitigate chip functionality and quality risks.

Discover the latest mixed-signal technologies and methodologies from Cadence Silicon Realization EDA solutions, such as:
  • Developing AMS behavioral and real number models
  • Power-aware mixed-signal simulation
  • Metric-driven SoC verification
  • Interoperability between analog and digital implementation platforms
  • Concurrent floorplanning and block design methodologies
You’ll also have a chance to network and discuss your mixed-signal challenges with Cadence experts, customers, and other attendees.
  • Analog/mixed-signal design engineers and layout designers
  • Analog/mixed-signal IP developers
  • Mixed-signal verification and digital implementation engineers
  • SoC integration and verification engineers
  • Engineering managers and executives
  • Anyone working on or considering advanced node SoC design projects
  • Those seeking technical expertise and examples of production-proven mixed-signal methodologies in use today
What will you gain?
  • Explore your options for implementing an integrated, interoperable mixed-signal solution that increases throughput, reduces risk, and improves design quality
  • Hear recommendations based on proven silicon successes and learn how to effectively deploy new methodologies in your design environment today
Agenda
8:30am Welcome
8:45am Mixed-signal verification challenges and solutions
9:15am AMS behavioral modeling
10:00am Analog and mixed-signal simulation and verification
11:00am Metrics Driven Verification of Mixed-Signal SoC
11:45am Power intent and verification in Mixed Signal
12:30pm Lunch
1:00pm Mixed-signal implementation challenges and solutions
1:30pm Mixed-signal implementation using a schematic-on-top methodology
2:30pm IR/EM analysis for mixed-signal designs
3:15pm Mixed-signal SoC integration using a netlist-on-top methodology
3:45pm Enabling interoperability through OpenAccess
4:15pm Wrap-up


Locations and dates
  • San Jose, CA: February 17
  • Chelmsford, MA: February 22
  • Austin, TX: February 23
  • Irvine, CA: February 24

Other locations and dates - Registration coming soon! Agenda and times will vary depending on location. Refer to local websites for details.

EMEA
  • Swindon, England: March 8
  • Grenoble, France: March 9
  • Munich, Germany: March 10
  • Milan, Italy: March 11
ASIA
  • Beijing, China: February 28
  • Shenzhen, China: March 2
  • Shanghai, China: March 4
  • Seoul, Korea: March 9
  • Hsinchu, Taiwan: March 11
  • Singapore: March 15
  • Yokohama, Japan: March 17

Questions About this Event?
Send email to events@cadence.com