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ARM Technology Conference 2010

Industry Conference  
09 Nov 2010 - 11 Nov 2010  
Santa Clara, CA  

This year Cadence has a major presence at ARM TechCon. Hear executives from Cadence and ARM discuss a revolution in the electronics industry and how to be part of the transformation. Visit the Cadence exhibits and get an overview of our collaborative efforts with ARM. See a provocative panel on systems and software on the exhibit floor and technical demonstrations in the area of system design and verification; a joint presentation with ARM about implementation of the Cortex-A15 core; and a demonstration of solutions for IP exploration and integration.

What you will see
Day 1 Chip Design Conference

Cadence and ARM Fireside Chat – The Evolving Electronics Industry
  • The electronics industry is going through a seminal shift. Major changes are happening right in front of our eyes. It is no longer about one company or one processor, but about the ecosystem and integrating interoperable hardware and software systems with an explosion of gadgets and applications. Cadence and ARM are playing key roles in leading the revolution with innovative products and new approaches to design. Attend this fireside chat between two of the industry’s most dynamic thought leaders to hear their views on the current state of EDA, how the two companies are working together today, and what’s next.
  • John Bruggeman, Chief Marketing Officer, Cadence
  • Simon Segars, EVP and GM, Physical IP Division, ARM
Tabletop #17
  • Cadence and ARM Working Together to Refresh the Electronics Industry
    ARM and Cadence engage in a wide range of design enablement programs for SoC, silicon, and system realization. From optimized Implementation Reference Methodologies (iRMs) to the broadest coverage of ARM Interface IP for verification, Cadence has optimized solutions for the latest ARM-based designs.
  • USB 3.0 Demonstration
    Developing an SoC requires high-performance IP that is qualified and integration-ready to reduce time to production, minimize cost, and improve product quality. See our demo and evaluation environment that uses a Xilinx Virtex-5 board configured as a device to show the performance of Cadence integration-optimized SuperSpeed USB 3.0 IP.
Sponsored session – Room #201
  • Keys to Silicon Realization of Gigahertz Performance and Lower Power ARM Cortex-A15
    This joint Cadence-ARM technical session will cover key considerations in the implementation of a dual core processor. We will describe advanced design techniques used in an RTL-to-GDSII digital implementation reference methodology. You will learn how to implement configurations of ARM’s advanced MPcores using a methodology that delivers gigahertz performance while minimizing power consumption. Techniques to be covered include synthesis strategy for best timing, placement strategies, clock-tree synthesis for on-chip variation reduction, power management, routing to facilitate DRC and DFM, and mixed-Vt optimization in signoff.
Technical papers
Days 2 and 3 System and Software Design Conference

Cadence booth #315
  • Cadence System Realization Demonstration
    Hear about the EDA360 industry vision and how the Cadence strategy for system realization includes higher levels of abstraction, integrated HW/SW development platforms, scalable verification performance extended to embedded software, and project management. You will learn about HW/SW co-design, early software development for ARM-based SoC designs, transaction-level modeling (TLM)-based design and verification, HW/SW metric-driven verification, and the Wind River collaboration.
  • Cadence System Realization Demonstration #2
    Hear about the EDA360 industry vision and how the Cadence strategy for system realization includes IC packaging solutions and how they are used to help semiconductor teams meet cost and schedule demands. Through a combination of advanced package design techniques, optimized chip-package-board implementation, and system-level analysis of timing, power, and signal integrity, Cadence enables IC/package design teams to cooperatively meet today’s dynamic and evolving IC packaging challenges.
Visit booth #208
  • Presentations:
    - ARM and relationships
    - Quick and easy IP exploration chip estimation and 3rd party IP decisions
  • Technology demonstrations:
    - Cadence Chip Planning System demonstration
    - Chip planning portal and IP ecosystem exploration
Panel – Thursday at 2:00pm; exhibit floor
  • Are System Developers Ready for Applications to Drive and Define a New World Order?
    Under pressure to improve both productivity and profitability, systems developers look for better ways to create, integrate, and optimize systems integration with the software and hardware. Can systems integration be effective when starting with components already geared toward the end application? What will be the impact on generally accepted processes and widely used tools of today? As integration issues and the importance of software become more pervasive, how can system designers and verification teams prepare themselves to ensure success in this new world order? This panel will debate many aspects of system realization and take a good hard look at key issues that will directly impact system-level design, and HW/SW integration
  • Panelists:
    - Dave Rusling, CTO Linaro, ARM
    - Peter Ryser, Director for System Integration and Validation, Xilinx
    - Michael McNamara, VP & General Manager, Cadence
    - Ashok Mehta, Sr. Manager, TSMC
    - Vahid Ordoubadian, Sr. Manager, Engineering Mobile Platform Group, Broadcom
  • Moderator: Ron Wilson, EETimes
Who should attend?
  • Engineers, engineering managers, executives, and individuals using ARM products
Cadence plays an essential role in helping the electronics industry realize advanced systems, SoCs, and silicon. ARM and Cadence have a strong ongoing partnership that drives the EDA360 vision and delivers optimized solutions. These include a full set of interoperable tools with ARM processors and physical IP, services, and methodologies from embedded Linux to GDSII, as well as a full suite of chip, package, and board co-design capability.

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