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Archived webinar - Where Does Power Intent Come From? Create and Debug Power Intent for Low-Power Designs

Original webinar date:
06 Dec 2010  
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Hundreds of early adopters of low-power design techniques have seen tapeout with a CPF-based flow. They use a trusted solution to verify the low-power intent of the design, from RTL through final routed design, and count on this solution to prevent chip failures.
  • Where does the power intent originate?
  • How do I create power intent before simulation? Synthesis? Implementation?
  • How do I verify that power intent is consistent with my design and my libraries?
  • How do I perform structural checks?
  • How do I ensure two versions of my design are equivalent (e.g., the design before power techniques and after)?
This webinar will describe real problems experienced in today’s designs and how to create and debug power intent in your proven power verification flow.

Questions About this Event?
Send email to webinar_info@cadence.com

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