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Archived webinar - When IP Collides, Brace for Impact on Timing Constraints and CDC! Verify and Manage Your Timing Constraints and CDCs!

Original webinar date:
03 Dec 2010  
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There is an emerging problem with timing and clock domain constraints. Design teams create timing constraints to drive synthesis, static timing analysis (STA), and post-route; yet problems with constraints and clocks appear as symptoms within each of those points in the flow. Meanwhile, to increase productivity, design teams leverage more internal and external IP to create complex designs. Suddenly, you’re not dealing with "your" timing constraints any longer, but constraints from a collection of sources. How are you sure the IP does not suffer from missing or overlapping timing constraints? And once you begin manipulating timing constraints, how can you be sure that your edits haven’t radically changed the timing intent of the design? Are your clock domain domains defined properly? This webinar will describe real problems experienced in today’s designs and describe a flow that provides an automatic means of avoiding chip failure.

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