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Archived webinar - Managing Parasitics in the Back End

Original webinar date:
01 Dec 2010  
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How is the physical implementation of my design going to affect my circuit performance? This is the age-old question that designers often struggle with when implementing a circuit.

In this webinar, we will go through a methodology referred to as "Rapid Analog Prototyping." This methodology shows how to efficiently and accurately generate physical information such as parasitics without having to wait for hand-crafted layout. We will use Pcells (parameterized cells) and MODGENs (module generation) in combination with custom place-and-route tools to quickly generate prototype layout, which can be used to accurately estimate physical aspects of a layout earlier in the design flow.

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