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Archived webinar - How To Completely Eliminate SoC Connectivity Bugs (Really!)

Original webinar date:
30 Nov 2010  
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Bugs from incorrect connectivity – whether they’re misconnected IP blocks inside an SoC or erroneous muxing of pad rings – can kill a chip as just easily as more sophisticated functional bugs. With internal connection points surpassing hundreds of thousands of nodes, the traditional approach of assigning detail-oriented summer interns to spot-check connectivity with some dynamic simulations is rapidly losing effectiveness. How do I ensure two versions of my design are equivalent (e.g., the design before power techniques and after).

In this webinar, we’ll show you how to apply formal verification technology to exhaustively prove with 100% mathematical certainty that all of your SoC’s internal and external pad ring connections are completely correct.

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