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Archived webinar - Are You Losing Sleep Over How to Perform Top-Level Mixed-Signal SoC Verification?

Original webinar date:
16 Nov 2010  
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Mixed-signal verification remains one of the biggest design challenges and verifying multi-million gate SoCs is not a trivial task. Mixed-signal design environments are not an entirely new ballgame, but it seems that neither analog nor digital engineers are completely prepared to enter each others’ areas of expertise. Thus the need for an integrated mixed-signal simulation and verification environment and mixed-signal behavioral modeling.

This webinar will introduce you to the Cadence mixed-signal verification environment that enables full-chip verification very close to digital speeds using real number models. You’ll also learn about mixed-signal behavioral modeling using Real/Wreal functionality in Verilog-AMS and SystemVerilog to achieve 500x performance boost for top-level SoC verification.

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