Engineering change orders, or ECOs, have become an indispensable method of integrating last-minute functional changes into a design without incurring huge penalties in turnaround time and subsequent tapeout delays. In the old days ECOs were done manually, relying heavily on designer know-how and equivalence checking to verify the netlist modifications. With the advent of new tools for automatic synthesis of ECO logic, engineers now rely more on tool and flow setup rather than netlist hacking in their favorite text editor. However, today’s modern implementation tools offer sophisticated optimization techniques that can make it difficult to create a small patch, and sometimes impossible to create a patch altogether. This webinar will discuss how automated ECO synthesis works, discuss techniques for debugging ECO synthesis problems (large patch size, failure to close timing after ECO synthesis, failure to find a valid patch), and finally discuss implementation flows that make the automated ECO synthesis process predictable.
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