Logic equivalence checking has been a standard in the digital implementation flow for more than 10 years, and has helped countless design teams in verifying implementation, optimization, and ECOs on thousands of tapeouts. With the ever-increasing complexity and variety of design transformations and optimizations, it is increasingly difficult to set up equivalence checking properly and more challenging for equivalence checking tools to verify datapath-intensive logic cones. This webinar will provide basic background knowledge on what equivalence checking is, how it works, and what causes false non-equivalence and aborts. We will then cover new techniques for debugging non-equivalence issues and preventing aborts in equivalence checking through coding style changes, implementation flows, and verification tool setup tips.
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