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Archived webinar - Analog Verification—How Do You Know Your Circuit is Right? Smart Verification!

Original webinar date:
17 Nov 2010  
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The complexity of analog and RF ICs and SoCs, combined with increasing cost pressures, means it is critical for engineers to efficiently verify complex sets of performance and operating conditions. Engineers are also expected to execute and document their verification plan with team members located around the world. Verifying designs for one operating condition or one performance at a time is neither feasible nor cost effective. It might result in design failure and, in many cases, losing the market to the competition.

Cadence resolves many of these issues by offering feature-rich, productivity-boosting verification methodologies. In this webinar, we will discuss the latest methodologies and techniques available from Cadence today to improve both verification productivity and design team collaboration.

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