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Archived webinar - TSMC Reference Flow 11: ESL Focus on High-Level Synthesis

 
Type:
Webinar  
Orignal webinar date:
03 Nov 2010  
Location:
Online  
  View Webinar »  

High-level synthesis is one of the key enables of higher productivity IP design and verification. TSMC has established a new ESL scope for their reference flow to help customers more easily adopt a methodology that increases productivity. Cadence contributed to the ESL reference flow, a part of which is enabling the adoption of high-level synthesis. The methodology focuses on creating high-level models in C, C++, or SystemC and using an interactive approach to understanding the resources and timing of the design.

This webinar will introduce the concepts of modeling for high-level synthesis and a repeatable approach to creating high-quality RTL designs that meet area, timing, and power constraints.


Questions About this Event?
Send email to webinar_info@cadence.com

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