A re-design or several weeks delay because of poor yield may mean the financial death of a project and the subsequent loss of market window opportunity. At 28nm and below, manufacturing challenges are such that minimum DRC rules fail to capture too many potential yield issues, whereas global application of relaxed DRC rules causes an unacceptable increase in design area. Alternatively, lithography simulation and analysis can be used to pinpoint litho-related yield issues (litho hotspots), but running model-based simulation is computationally expensive, which increases the design cycle when inserted early on in design.
GLOBALFOUNDRIES recently announced an innovative DFM approach called DRC+, which is more than 100 times faster than traditional litho simulation. DRC+ leverages fast 2D pattern matching to search the design for 2D patterns that are potential yield detractors and mark them for fixing with relaxed DRC rules. The targeted application of relaxed DRCs at these critical locations improves yield without sacrificing design area.
To enable DRC+ for designers, GLOBALFOUNDRIES has made available the industry’s first 28nm pattern library of potential yield detractors. Cadence has been an early development partner with GLOBALFOUNDRIES in the development of the DRC+ flow, which leverages Cadence pattern classification technology to classify yield detractors into pattern families.
This joint technical webinar will describe what, when, why, and how designers can incorporate DRC+ into an existing digital implementation flow to achieve DFM signoff at 28nm and below. With Cadence pattern matching and automated fixing built into Encounter tools, designers can quickly identify and fix DRC+ errors, thereby avoiding potential manufacturability issues down the road. By capturing these issues early in the design flow, DRC+ provides Encounter place-and-route engineers peace of mind that their SoC design is DFM-clean.
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