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Archived webinar - Multi-Gigabit Serial Link Design and Analysis

Original webinar date:
14 Oct 2010  
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While multi-gigabit serial links have brought huge benefits to system price and performance, correct implementation of them in hardware has made compliance and interoperability testing a challenging experience. Multi-gigabit SerDes now feature elaborate equalization schemes that have been met with new modeling and analysis technologies. Modeling SerDes along with careful characterization of serial link interconnect are the cornerstones to a revolutionary simulation technology known as channel analysis (CA), featured in Cadence® Allegro® PCB SI GXL. CA can quickly simulate 10,000 bits in seconds, allowing engineers to design and quickly adjust multi-gigabit interfaces so that they are compliant with industry standards.

This webinar will provide an overview of the issues faced in creating multi-gigabit serial links and will show you how using Allegro PCB SI GXL can solve these challenges. The webinar will be broken up into the following focus areas:
  • S-Parameters and advanced via modeling
  • Signal quality screening
  • Channel analysis
  • Algorithmic modeling (AMI) for SerDes
Who should attend?
  • Current users of Allegro PCB SI
  • Multi-gigabit layout designers
  • SerDes IC designers

Questions About this Event?
Send email to webinar_info@cadence.com

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