Over the past few years, the discussion of hardware verification languages (HVLs) has come full circle. At first, verification teams tried to assess the strengths and weaknesses of individual language features with the goal of creating their own verification libraries and environments, but generally without the context of a reuse methodology. As these groups became more sophisticated and sought to exchange and reuse verification IP (VIP), they coalesced on the two IEEE standardized verification languages—1800 SystemVerilog and 1647 e
—and moved toward the industry-supported methodologies and libraries built with these languages. With the advent of a single methodology implemented in both languages—OVM/UVM multi-language—the discussion has returned to HVL features. But now with the reuse methodology known, a true “apples vs. apples” comparison can be made.
Another classic comparison is the efficiency of coding, but in the methodology context, this is split between the test writer and the verification IP developer. When e
and SystemVerilog are set into these methodology elements, feature comparisons like AOP vs. OOP, the use of factory patterns, randomization/generation schemes, SVA vs. e
assertions, and tool support become apparent and compelling.
The choice of HVL was once a murky process that resulted more in a vendor preference than an optimized technology selection. With HVL standardization and the popularity of consistent, open, interoperable methodologies, verification engineers can fairly debate the merits of languages. Teams can now base their selection on technology merits and maximize productivity, predictability, and quality. The following topics will be covered in the webinar:
- Common language misconceptions
- Verification characteristics that make languages important
- Important technical aspects to consider for each language
- Which language fits best, and where?