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Archived webinar - TLM-Driven Design and Verification Solution and Methodology

Original webinar date:
14 May 2010  
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Semiconductor companies are feeling ever-more pressure to develop SoCs with software in less time, and to respond quickly to changes from their OEM customers. Realizing today’s complex SoCs efficiently and cost-effectively requires that developers move to a higher abstraction for design and adopt transaction-level modeling (TLM) approaches. A comprehensive TLM solution increases productivity and improves system-level quality, helping engineers respond to increasing and fluctuating market demands. Cadence offers a comprehensive TLM-driven design and verification solution, along with adoption services, that customers are implementing successfully.

This webinar explains:
  • The key challenges that demand a change from RTL as the source entry point
  • Critical solution requirements for a TLM-driven IP design and verification flow
  • The significant reuse benefits of such a flow
  • The key capabilities of the Cadence solution that enable success
  • The Cadence products that deliver these benefits

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