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Archived webinar - Addressing DDR3 Timing Challenges

 
Type:
Webinar  
Orignal webinar date:
09 Jun 2010 (10:00am - 11:00am PDT)  
Location:
At your desktop  
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Addressing DDR3 Timing Challenges

See the value of an integrated constraint-driven design and analysis environment where changes can easily be made to the design and reanalyzed without having to translate design data. This webinar will review the signal integrity (SI) design flow, focusing on the timing analysis phase. A DDR3 design will be analyzed within Allegro PCB SI, and integration with EMA TimingDesigner will allow us to detect, correct, and update the timing violation within the Allegro PCB SI environment.


Questions About this Event?
Send email to webinar_info@cadence.com

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