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Archived webinar - Plan Your Design to Save Time and Reduce Layer Counts

 
Type:
Webinar  
Orignal webinar date:
20 May 2010  
Location:
Online  
  View Webinar »  

Increasing use of standards-based interfaces (DDRx, XAUI, PCI Express) are making it harder to finish routing the design in a predictable manner. Decreasing pin pitches along with an increasing number of large pin-count devices are forcing PCB designers to add layers that in many cases are unnecessary. This webinar will show users how planning your design using Allegro Interconnect Flow Planning technology can shorten design time and reduce the number of layers.


Questions About this Event?
Send email to webinar_info@cadence.com

View Webinar »