Get highly technical insight into the advanced low-power techniques that engineers are challenged with today. Hear from Cadence low-power R&D and Services architects about current and next-generation advanced low-power techniques. Join us to discuss low-power and energy efficient design with technical experts. Achieve project tape-out goals by helping incorporate low-power design techniques and define fully-automated low-power design methodology. Optimize performance, reduce costs and mitigate both schedule and chip functionality/quality risks. During the jam-packed technical agenda, our low-power architect members will share their expertise and stories-best practices and proven capabilities that you can adopt to design energy-efficient wireless and wired electronics.
· Anyone interested in getting a technical view of low-power design topics straight from technical experts
· Logic design, verification, and digital implementation engineers and managers; systems architects and executives
· Anyone working on or considering an energy-efficient design project
· Those seeking technical expertise, knowledge of ecosystem capabilities, and examples of production-proven low-power methodology in use today
Through the eyes and minds of Cadence R&D architects, explore your teams' options for managing power throughout the entire design process, receive methodology recommendations based on proven silicon success, and learn how you can effectively deploy those methodologies in your design environment today.
Shanghai, Oct 26, 2009Beijing, Oct 28, 2009Shenzhen, Oct 30, 2009
Why is power management so important?
Different types of power consumption
Power management techniques in use today
Customer case study #1
Early power estimation and exploration
Hierarchical IP low-power methodology
Closed loop verification
Major physical implementation challenges in low-power design
Customer case study #2
Hitting the low-power design target
Very advanced low-power technology
Summary and Q&A
Wrap up and leave
About the technology presenters
Dr. Pinhong Chen is an Engineering Director with Cadence. He is primarily responsible for the low-power and the clock tree synthesis features in SoC Encounter and Encounter Digital Implementation Systems. He is also the main architect to define CPF and its support in P&R.
Pinhong holds a B.S. degree and an MSEE degree in Electrical Engineering from National Taiwan University, and a Ph.D. degree from CAD group, EECS department of UC Berkeley.
From 1995 to 2001, he worked as an EDA consulting staff in the design service department of TSMC. In 2001, he joined Silicon Perspective Co., which was acquired by Cadence in 2002.Luke Lang is a Sr. Technical Leader in Cadence's Low-Power Solutions group focusing on low-power architecture, methodology, and deployment. Before Cadence, Luke worked on ASIC and mixed-signal IC design and application at TI, Philips Semiconductor, and IBM. Luke received a BSEE degree from Santa Clara University and a MSEE degree from Stanford University. He holds two U.S. patents.
Chinese and English
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