Logic design teams hate to hear that their chip design project is at risk of not meeting its goals or schedule because of routing congestion. The fate of the project is out of your hands and there is nothing you could have done to prevent this. Or is there?
This webinar will outline some new automated techniques built into synthesis that identify, fix, and even prevent congestion issues, helping you take back control of your project’s success.
Presenter
Ankush Sood, Principal Product Engineer
Questions About this Event?
Send email to webinar_info@cadence.com