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Mixed Signal IC Design Seminar

20 Jul 2009 9:30 AM  

Registration Closed
Let's talk technical about mixed signal design
Expert-to-expert discussions

Get highly technical insight into the advanced mixed signal techniques that IC design engineers are challenged with today. Hear from Cadence mixed signal R&D and Services architects about current and next-generation advanced mixed signal techniques. Join us to discuss mixed signal design with technical experts.
Achieve project tape-out goals by helping incorporate mixed signal design techniques and define automated mixed signal design methodology. Optimize performance, reduce costs and mitigate both schedule and chip functionality/quality risks.
During the jam-packed technical agenda, our mixed signal architects will share their expertise and stories-best practices and proven capabilities that you can adopt to design energy-efficient wireless and wired electronics as well as our solution roadmap.

Who should attend?
  • Anyone interested in getting a technical view of mixed signal design topics straight from technical experts 
  • Mixed signal design and implementation engineers and managers; systems architects and executives
  • Anyone working on or considering a mixed signal design project
  • Those seeking technical expertise, knowledge of ecosystem capabilities, and examples of production-proven mixed signal methodology in use today

What you will learn
Through the eyes and minds of Cadence R&D architects, explore your teams' options for managing mixed signal design challenges throughout the entire design process, receive methodology recommendations based on proven silicon success, and learn how you can effectively deploy those methodologies in your design environment today.

9:00 AM Reception
9:30 AM Welcome and introduction
9:35 AM Mixed Signal Design trends, challenges and Cadence solution Roadmap
10:20 AM Speed up your Spectre/Multi-Mode Simulation without sacrificing accuracy and no change in the use model
11:05 AM Cadence Digital Mixed-signal Solution and Low Power Solution
11:50 AM Lunch
12:50 PM Mixed Signal Implementation
1:50 PM break
2:20 PM Parasitic Extraction and Post-Layout Verification for Analog/Mixed-signal Designs
3:20 PM Virtuoso IC 6.1 front-to-back flow
4:20 PM Summary and Q&A
5:00 PM Wrap and Leave

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