Cadence is hosting a series of webinars to help to increase its customers’ productivity by transferring knowledge about its technologies and methodologies in key focus areas.
| Original Webinar Date |
Title |
Presenter |
| Tuesday 23 February |
Mixed-Signal Simulation for Analog Designers Read More» |
Marcel Ahmedzai |
| Thursday 25 February |
Understanding INCA_libs Read More» |
Kevin Chong |
| Tuesday 2 March |
Debugging Techniques for APIs and SDF Read More» |
David Henly |
| Thursday 4 March |
Encounter® Library Characterizer – Targeting the right process corners for your designs Read More» |
Keith Tunstall |
| Thursday 11 March |
Low Power IP Integration and Macro Modelling with CPF Read More» |
John Longvill |
| Tuesday 16 March |
What’s New in Allegro 16.3 PCB Editor? Read More» |
Andrew Windscheffel |
| Thursday 18 March |
Synthesis: The Need for Predictability Read More» |
Bupendra Bechar |
| Tuesday 23 March |
New Layout Productivity Features in Virtuoso® IC6.1.4 Read More» |
Daniel Nelhams |
Mixed-Signal Simulation for Analog Designers
Original date: Tuesday 23 February 2010
Duration: 1 hour
Presenter: Marcel Ahmedzai
When Analog designers are given the task of running mixed-signal simulations for a mixed Analog and Digital design, they are given the digital RTL/Netlist from the digital designer and are tasked with finding a solution simulating both the Analog and Digital parts together. There are many ways to include the digital RTL/Netlist into the mixed-signal design, but which one should one choose? For example, how do the digital blocks interact with the multiple supplies of the analog design? Once the digital RTL/netlist is brought into the mixed-signal environment and a simulation is run with AMS designer there are often warnings and errors that need to be addressed. What do they all mean? How can they be solved?
This webinar will cover various methods of including digital RTL/Netlist and will provide methods of resolving typical warning/error messages seen.
View webinar recording»
Understanding INCA_libs
Original date: Thursday 25 February 2010
Duration: 1 hour
Presenter: Kevin Chong
Have you ever wondered what IUS writes into ./INCA_libs? At this webinar we will explain the implicit steps IUS does when creating and reading the INCA_libs directory.
- Logical library naming conventions
- Working with pre-compiled libraries
- irun and ncsc_run directory structure differences
- Switching between single step (irun) and multi-step (ncvlog/ncelab/ncsim)flows
- Useful utilities
Debugging Techniques for APIs and SDF
Original date: Tuesday 2 March 2010
Duration: 1 hour
Presenter: David Henly
This is a two-part webinar focused on debugging elaboration and run-time errors in user defined shared libraries and SDF simulations.
Part 1: IUS has many different APIs (Application Programming Interfaces) - PLI, VPI, DPI, VHPI, FMI. Debugging elaboration crashes can be challenging, with users resorting to commenting out code, adding copious printf statements and other crude methods to identify the problem area. Fortunately a number of methodologies exist to help diagnose problematic code, and speed up the debug process. This section examines the use of gdb and purify tools in the debug flow.
Part 2: Gate level simulations involving SDF delays often run in to problems with annotation – mismatched cell libraries, subtle differences in the way layout tools write out sdf data. Here we look at the steps the engineer should use to pinpoint issues.
View webinar recording
»
Cadence Encounter Library Characterizer – Targeting the right process corners for your designs
Original date: Thursday 4 March 2010
Duration: 1 hour
Presenter: Keith Tunstall
To design silicon chips today, engineers need to use library files containing timing, power, signal integrity, and statistical information at appropriate Process, Voltage & Temperature (PVT) corners. Libraries provided with design kits typically cover a fixed range of operating conditions which limits the scope designers have to save power by reducing supply voltages or work at extremes of temperature.
The library re-characterization capability within the Cadence® Encounter® Library Characterizer solution is an ideal way to generate new voltage and temperature corners to provide accurate libraries for the design process.
View webinar recording»
Low Power IP Integration and Macro Modelling with CPF
Original date: Thursday 11 March
Duration: 1 hour
Presenter: John Longvill
Power is now a major consideration for 90nm and below designs. With this comes the problem of integrating IP designed for low power. How do you ensure that the IP’s power modes are compatible with the designs power modes? Does the IP contain power switches, isolation cells state retention cells?
The Common Power Format (CPF) is a method for capturing power intent for a design. CPF Macro models and hierarchical flow enable low power IP to be developed independently to its final application. The internal power intent of the IP can be defined ensuring correct integration.
In this webinar we look at defining CPF models for IP and the verifying its integration into the final application.
View webinar recording»
What’s New in Cadence Allegro PCB Editor 16.3?
Original date: Tuesday 16 March
Duration: 1 hour
Presenter: Andrew Windscheffel
This webinar will cover the new features in Allegro® PCB Editor 16.3:
- 3D PCB view
- Mirror Image
- Design Miniaturization
- HDI
- Component Placement
- Miscellaneous features
View webinar recording»
Synthesis: The Need for Predictability
Original date: Thursday 18th March
Duration: 1 hour
Presenter: Bupendra Bechar
At 130nm and below, wires dominate the delay equation, and it gets worse with each process generation. Synthesis tools are tasked with creating an optimal logic structure, but they still rely on fanout-based wireload models that treat all wires for a given block size as the same.
The reality is that every wire is unique. In a typical chip, 80-90% of wires are local interconnect, but even those can have different characteristics depending on the nature of the block (shape, size, density, datapath, random logic, etc). The 10% wires that represent global interconnect are the real timing headaches.
So many wireload models have become so far off the mark that many designers just ignore wire effects altogether – not a better solution, just a faster path through non-convergent iterations. The real challenge is to give synthesis tools better wire information…however how do you model wires before you have gates?
View webinar recording»
New Layout Productivity Features in Cadence Virtuoso IC 6.1.4
Original date: Tuesday 23 March
Duration: 1 hour
Presenter: Daniel Nelhams
Traditionally custom layout has been a manual and time consuming process. See how new functionality within Virtuoso® IC 6.1.4 can increase productivity by reducing the number of mouse clicks, make intelligent choices, and aid a layout designer to complete everyday tasks in a smarter and easier fashion. The new features showcased at this webinar will be:
- Bus Labelling
- Smart Ruler
- Smart Copy
- Layer Palette
View webinar recording»