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Low-Power Technology Summit Proceedings 

 
Type:
Cadence Event
Date:
October 18, 2012
Location:
Cadence Design Systems, Bldg. 10 auditorium, San Jose, CA
 

On October 18 Cadence held a Low-Power Technology Summit. Experts from Cadence and other leading companies presented the latest low-power design methodologies. If you missed the event, you can still view the material via the below archived proceedings.

Learn more about the Low-Power Solution

Agenda
Topic Speaker Proceedings
Welcome and Opening Remarks Dr. Chi-Ping Hsu, Cadence View presentation
View video
Keynote Presentation Professor Jan Rabaey,
UC Berkeley
View presentation
View video
Low-Power Solution Technology Update Pete Hardee, Cadence View presentation
View video
Low-Power Design with ARM® Physical IP and POP™ IP Sathya Subramanian, ARM View presentation
View video
Low-Power Verification in Mixed-Signal Designs
Cadence technology and customer experiences
Shekar Chetput and
Luke Lang, Cadence
View presentation
View video
Customer Case Study: Low-Power Design Experiences on Kinetis Anis Jarrar, Freescale View presentation
View video
Power Formats: Standards and Support Update Dr. Qi Wang, Cadence View presentation
View video
Panel Discussion and Q&A Moderator: Richard Goering View video