Design Planning with Allegro Interconnect Flow Planner
Quickly capture and adhere to routing intent for highly constrained, high-density, standards-based designs
Increasing use of standards-based interfaces (DDRx, XAUI, and PCI Express, to name a few) are making it harder to route a design in a predictable manner. Shrinking pin pitches along with an increasing number of large pin-count devices are forcing PCB and IC package designers to add layers that, in many cases, are unnecessary. These highly constrained, high-density designs can take significant time to plan and route. Add to this the complexities of new signaling levels and topology requirements, and it’s no wonder that traditional CAD tools fall short of capturing and acting on specific routing intent.
Allegro Interconnect Flow Planner
Cadence® Allegro® Interconnect Flow Planner provides the technology and methodology to not only capture, but adhere to, routing intent for dense designs with highly constrained, standards-based interfaces. After capturing design intent, its hierarchical interconnect flow planning architecture provides feedback from the route engine, significantly shortening design cycle time and reducing the number of layers. Users can, for the ﬁrst time, leverage their expertise and put design intent into a tool that understands what they want—natively.
Through the Allegro Interconnect Flow Planner architecture, you can create abstracted interconnect data, quickly converge on a solution, and validate it with the route engine. Interconnect abstraction reduces the number of elements the system has to deal with—from potentially tens of thousands down to hundreds—which also reduces the manual interaction required. Since you see fewer visual elements in the interconnect ﬂow plan, there are fewer elements for you to physically manage.
Using the abstracted data, Allegro Interconnect Flow Planner accelerates the planning and routing process by providing a visual/spatial map of the open area in relation to the data and your design intent. The route engine can then deal with the details of the routing, adhering to the speciﬁed intent, without requiring you to both visualize and solve the interconnect problems at once.
This ease-of-use over other design tools means that you can converge on a successful interconnect solution far faster and easier than ever before, reducing design cycle time through increased productivity.
- Predictable design cycles for dense, highly constrained designs through intelligent, iterative planning and routing of interconnects
- Shorter design time for complex, highly constrained designs
- Reduced number of layers required to route a dense, highly constrained PCBs or IC packages