Allegro Timing Closure Environment
As data rates increase and supply voltages decrease in today’s advanced interfaces like DDR3/DDR4, PCI Express, and SATA, PCB and IC package designers have to spend more time to ensure signals in an interface meet timing requirements. With increasing density, the effort to get to timing closure – ensuring all signals meet timing requirements – can increase significantly. Layout designers need new tools to meet this increasingly complex challenge.
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Allegro TimingVision Environment
Allegro® TimingVision™ technology provides an innovative and unique environment that allows you to graphically see real-time delay and phase information right on the routing canvas. Traditionally, evaluating current status of timing/length of a routed interface requires numerous trips to Cadence® Allegro Constraint Manager and/or use of the Show Element command. Using an embedded route engine to evaluate complex timing constraints and interdependencies amongst signals shows the current status of a set of routed signals – a DDRx byte lane or a complete DDRx interface – via custom trace/connect line coloring, as well as stipple patterns and customized data tip information to define the delay problem in the simplest terms possible. With the embedded route engine, the Allegro TimingVision environment provides real-time feedback during interactive editing and enhances your ability to develop a strategy for resolving timing on large buses or interfaces such as DDRx and PCI Express. Coupled with Auto-interactive Phase Tuning and Auto-interactive Delay Tuning capabilities, this environment lets you speed timing closure of high-speed PCB interfaces by up to 67%.
Auto-interactive Phase Tune (AiPT)
Differential pairs in an interface like DDRx require you to match static as well as dynamic phases. Matching phases for all differential pairs in an interface is a necessary first step before tuning and matching the rest of the signals. Auto-interactive Phase Tune (AiPT) automatically matches dynamic and static phases for the selected differential pairs. It works with a set of parameters that provides you with several options for trace lengthening or shortening as well as pad entry/exit options. With AiPT, you can significantly shorten the time to match static and dynamic phases for differential pairs.
Auto-interactive Delay Tuning (AiDT)
Delay tuning for signals for interfaces like DDRx takes up too much time when using traditional, manual methods. Auto-interactive Delay Tune (AiDT) automatically generates tuning patterns on a user-selected routed byte lane or interface based on user-defined timing constraints and tuning parameters. AiDT computes the required length for the connections to meet timing constraints, and utilizes controlled push/shove techniques when adding tuning patterns.
- Helps you visualize real-time delay and phase information right on the canvas
- Shortens time significantly to implement standards-based interfaces
- Reduces frustration over unnecessary trial-and-error in fixing timing issues