Doulos is the global leader for the development and delivery of market leading training solutions for SoC, FPGA and ASIC design and verification. Our business ethos is 'service through excellence' which, when combined with our world-leading independent know-how, makes Doulos the ideal training partner.
Our commercial independence and industry wide partnerships enable Doulos to bring significant added value to our clients. This also enables Doulos to make a unique contribution to the EDA industry as a whole in the area of emerging design and verification methodologies.
Doulos is pleased to partner with Cadence to provide leading edge training solutions in the context of the Cadence verification product range and supporting methodologies.
Customers can access training using Cadence tools on the Doulos scheduled program of classes in various locations in the US and Europe; and team based custom training is provided by Doulos subject-matter experts worldwide at customer locations.
Subjects include verification methods based on e, SystemVerilog, SystemC, PSL, Verilog and VHDL. Check out the scope of training
Incisive Plan-to-Closure Methodology Qualified
Incisive Plan-to-Closure Methodology—Qualified Verification Alliance members have demonstrated expertise in one or more of the methodology’s four key elements: verification planning and management, the Universal Reuse Methodology, assertion-based and formal verification, and/or system-level verification. Doulos provides training worldwide for verification planning and management and universal reuse.
| Assertion Based, Coverage Driven, Formal, Plan To Closure Methodology, Reuse Methodology, System Level Methodology, Services, Training, |
|e, Specman, System Verilog, System Verilog Assertions, PSL, OVL, System C, C++, Verilog, VHDL|
|ASIC, Automotive, Consumer Electronics, Defense, Low Power, Microprocessor, Multi-media, Networking, Storage, Telecom, Wireless|