CoFluent Design www.cofluentdesign.com
CoFluent Design provides system-level modeling and simulation tools for executing use cases and analyzing performance of embedded devices and chips. CoFluent Studio generates SystemC-based transaction-level models (TLMs) from UML diagrams and standard C that describe complex multi-OS, multi-core embedded systems. CoFluent Reader enables efficient exchange of executable specifications with all project stakeholders and contractors.
CoFluent Design plans to adapt its simulation library and environment to support hardware/software co-verification of SystemC design and software drivers using the Universal Verification Methodology (UVM) and Cadence Incisive SystemC simulation and Incisive Software Extensions.
Designers use CoFluent Studio to create executable specifications of an integrated circuit (IC) by modeling its functionality and use cases with either UML or the CoFluent language. Blocks, data, and control flows are described in graphics. Algorithms are defined with ANSI C code and given an execution time budget (number of cycles). Simulations are driven by use cases for validating the model behavior and time properties. The automatic SystemC TLM code generation allows reuse of IC and use-case models for validating the RTL implementation within the Cadence environment. A SystemVerilog testbench can also be used to validate in parallel the reference SystemC TLM and its RTL implementation written in VHDL or Verilog within the Cadence environment.
Additional solution information
“System conceptualization and implementation need to be connected,” said Stephane Leclercq, CEO of CoFluent Design. “Our work with Cadence will bring together system modeling, implementation, and verification to bridge the worlds of system specification and silicon.”