Cadence and ARM have a long history of collaborating closely on complete system-to-silicon solutions, with many recent milestones:
Cadence, ARM, and IBM
announced the tape out of industry's first 14nm FinFET Cortex®-M0 processor.
Cadence and ARM announced the tape out of 20nm ARM Cortex™-A15 MPCore™ processor.
Cadence and ARM announced our early collaboration on the latest Cortex™-A15 multi-core processor to deliver an optimized implementation methodology for ARM’s early access customers (such as Texas Instruments).
Cadence and ARM continue to working closely on AMBA® 4 verification IP with particular emphasis on the AMBA 4 Coherency Extensions (ACE) protocol.
At DAC in June 2011, ARM announced ACE simultaneously with the Cadence® announcement of the ACE verification solution.
For hardware/software co-development, the Cadence
System Development Suite (SDS) provides a set of continuous engines from transaction-level Virtual Prototypes though RTL Simulation, Hardware Acceleration and Emulation to FPGA-based prototyping. All the SDS engines are able to execute ARM processor IP (from Fast Models to RTL) and interface to ARM Development Studio 5 for embedded software development, making it the industry’s most comprehensive environment for hardware/software co-development of ARM based SoCs and Systems.
The market for high-performance processor core-based SoCs is growing, and so is the need for chip implementation solutions for that segment. Demanding system specifications dictate using advanced process technologies.
Early and tight collaboration with ARM and leading foundries ensures that the Cadence RTL-to-GDSII flow is silicon-proven and compatible with leading-edge libraries achieve designs with aggressive GHz+ performance at the lowest possible power consumption. The ARM-Cadence Encounter® Implementation Reference Methodology (iRM) is a proven implementation flow that delivers design techniques, from RTL to GDSII, for ARM-synthesizable processors. The iRM reduces time to silicon with predictable power, performance, and area results.
The Cadence and ARM lock-in-step R&D collaboration project for the Cortex-A15 multi-core processor ensures:
Development of an optimized Cadence unified digital flow, which challenges PPA targets for state-of-the-art implementation of dual-core Cortex-A15 processors
Early commitment and joint work among Cadence, ARM, and Texas Instruments (the fist licensee of Cortex-A15) to deliver out-of-the-box production-proven flows
Utilization of the ARM-Artisan® Processor Optimization Package (POP), which includes a (standard cell library) High-Performance Kit and Fast Cache Instance RAMs targeting the Common Platform 32nm (cp-cmos32LP) library
Strong experience in implementing Cortex-A15 processor cores based on early access to Cortex-A15 RTL since mid-2010
ARM and Cadence expertise and “lessons learned” rolled into software releases/ updated flows
Cadence support for all Cortex-A15 licensees in developing and implementing next-generation devices
Physically-aware synthesis, including optimal cost group/mux optimization strategies
Advanced DFT capability with highest ATPG coverage
Early exploration prototyping and floorplanning
Comprehensive CPF-based power management, including power gating and multi-voltage
Clock concurrent optimization (CCopt) technology for better timing closure
Physically-aware clockgate cloning
Pre- and post-route optimization with a strong focus on total negative slack
Advanced analysis engine (AAE) for incremental delay and SI calculation
Newly developed high-speed core option
Better quality of results for high-performance processor cores
Higher performance for SoCs with integrated high-speed cores
Better supportability and scalability – jointly qualified and tested by ARM and Cadence, and supported in the latest ARM iRMs
Excellent Cadence support team, mentored by the high-speed core R&D Tiger team that worked closely with ARM on CA-15 iRM
Easier to use – simplified use model improves productivity and time to market
Webinars and Events
To address today’s biggest challenges in system-level IP integration and verification, such as earlier software development, Cadence collaborates with ARM to deliver a complete system development and hardware/software verification platform for customers developing ARM processor-based systems. The joint solution includes integration with ARM Fast Models for virtual prototyping, pre-established emulation flows for earlier hardware/software integration and software validation, and a faster path to RTL and verification closure. All the SDS engines enable efficient hardware/software co-development by interfacing to the ARM Development Studio 5 and RealView debug solutions.
Key components of the joint solution feature the Cadence System Development Suite for hardware/software co-verification and flows to address system-level integration, low-power verification, and metric-driven verification using the Universal Verification Methodology (UVM) standard that allows customers to build powerful, open, and reusable system-level verification environments. Mature, industry-standard verification IP (VIP) for all the key AMBA protocols, as well as transaction-based acceleration and efficient performance analysis of the ARM based interconnect are also supported.
Features and benefits
Virtual prototype development for ARM-based systems using Fast Models with Cadence Virtual System Platform, connected to ARM DS-5 and RealView® Development Suite
Most mature VIP and
accelerated VIP for all AMBA protocols (ACE, AXI, AHB, APB) Unique Interconnect Monitor (ICM) to verify ARM interconnect including CCI-400 with coherency
Enhanced interoperability of ARM tools and IP (including ARM DS-5 and RealView® Development Suite, Fast Models, and VSTREAM transactor) with Cadence Incisive® Enterprise Simulator and the Palladium® XP Verification Computing Platform
Hardware/software UVM testbench automation and embedded software tracing for ARM-based SoC development using Incisive Software Extensions
Technologies Webinars and Events