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EMEA Training Course Detail 

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Availability
DatesLocations
12 May 2014 - 13 May 2014Vélizy-Paris, FranceExpress Interest »
02 Jun 2014 - 03 Jun 2014Bracknell-London, United KingdomExpress Interest »

Course TitleVirtuoso Schematic Editor vIC.6.1.5
Course CategoryCustom IC Design – Virtuoso
Duration2 days
Course IDES_84443_IC.6.1.5
Product Version6.1.5

“Efficient course for me to get started with the Virtuoso environment. I appreciated the small group and that I had enough time to do the labs.”
(Stefan Ganserer, Intel, January 2014)

“We had a very good trainer for the course. Every question was answered by him and he explained all topics very well. My overall impression is that Cadence provides very good courses.”
(Andrea Stueckler-Riavec, MBA, Intel Austria, January 2014)

Course Description

In the Virtuoso® Schematic Editor course, you learn to create and edit schematics for use with the suite of Cadence® simulation and layout tools. You use the Verilog® In and SPICE In translators to generate netlists and symbols. You place instances, wire schematics, use hierarchical design, run netlist creation and simulation, add rules using the Constraint Editor, create inherited connections, open and use window assistants, and generate layout instances from the schematic.

Learning Objectives

After completing this course, you will be able to:

o   Create schematics, symbols, libraries, and components for use in your designs

o   Use bindkeys to increase your efficiency and automate repetitive tasks

o   Edit component properties and configurations

o   Understand flat and hierarchical schematics

o   Create netlists and run simulations

o   Run Verilog In and SPICE In to generate netlists and schematic symbols

o   Establish inherited connections to allow for variables to establish design properties on hierarchical instances

o   Add constraints in schematics for use in the layout

Software Used in This Course

o   Virtuoso Schematic Editor XL

o   Virtuoso Analog Design Environment L

o   Virtuoso Schematic Editor L

Software Release(s)

o   IC615, MMSIM 7.2

Course Agenda

Note that this course can be tailored to better meet your needs – contact the Cadence training staff for specifics.

Day 1

o   Introduction

o   Basic schematic capture

o   Netlisting in the Spectre® environment

o   Symbol generation

o   Using Verilog In

o   Using SPICE In

o   Navigating the hierarchy

Day 2

o   Using tabs, workspaces, and assistants

o   Advanced schematic capture

o   Generating netlists and simulation

o   Using the Constraint Editor

o   Generating layout

o   Working with inherited connections

Audience

o   Analog/Mixed-Signal IC Designers

o   Analog Designers

o   Analog IC Designers

o   Chip Designers

o   Custom Circuit Designers

o   Design Engineers

o   Designers

o   IC Designers

o   RF Designers

Prerequisites

You need to be familiar with schematic entry, simulation, and physical design.

Cadence software as listed above installed and licensed

Related Courses

 Virtuoso Analog Design Environment v IC6.1.6