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EMEA Training Course Detail 

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Course TitleCadence Library Characterization and Validation v3.1p3
Course CategoryCustom IC Design – Virtuoso
Duration2 Days
Course IDES_85041_3.1p3
Product Versionv3.1p3

"Learnt a lot. Labs had been well-prepared. All my questions were answered professionally, no open questions. After the training we had some time to set up something we didn't send for custom lab preparation. Thanks to the presenter, it worked on-the-fly."
(Oliver Schrape, IHP Microelectronics, June 2015)

Course Description

During this course, the student will learn the basic skills necessary to characterize and validate standard cell libraries using both Cadence Library Creation and Cadence Library Validation software tools. The course consists of both lecture and labs.

Learning Objectives

After completing this course, you will be able to:

o   Create Liberty, Verilog, Vital and datasheet library views.

o   Characterize Standard Cells for timing, power and noise.

o   Use different algorithms for characterizing timing, power and noise.

o   Validate Liberty libraries for correctness, consistency and accuracy.

o   Explore differences between library data.

o   Identify and Debug failed characterization data.

Software Used in This Course


Software Release(s)

o   3.1p3

Course Agenda

Note that this course can be tailored to better meet your needs – contact the Cadence training staff for specifics.

Day 1

o   About this Course

o   Introduction to CLC

o   Building a Library from Scratch

o   Library Re-characterization

o   Characterization Methods for Timing, Power and Noise

o   Creating Current Source Mode

Day 2

o   Validating Libraries with CLV

o   Debugging Characterization Issues


o   Design engineers or CAD engineers who are responsible for creating libraries to use in
front-end design flows.


You must have:

o   A working knowledge of Liberty Syntax.

o   An understanding of transistor level simulation and syntax.

o   A basic knowledge of TCL programming.