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The usage of advanced process nodes and the scale of integration of smaller and faster transistors have resulted in ever-increasing power dissipation. Whether the need to reduce power consumption comes from extending battery life, increasing a chip's reliability by reducing the heat that's produced, or environmental concerns, power efficiency is a vital design consideration.
This offering combines tools, methodology, best practices and design to provide a cost effective and low risk program enabling teams to bridge knowledge gaps associated with significant technology and team transitions. It replaces the typical training techniques that usually include:
- Learning on-the-fly, or learning from mistakes
- Ad-hoc training from manuals, web help, and so on
- Reduced productivity of experienced staff that will need to spend time mentoring others in power efficient design
AudienceDepending on the audience, this program can be offered in full or in tracks:
The Complete Program: This program is intended for those Design Engineers and Place and Route Engineers who will be managing, designing, implementing, and verifying a power efficient design.
The Logic-Design Track: This program is intended for those front-end engineers who will be architecting, simulating, synthesizing and verifying a power efficient design.
The Digital-Implementation Track: This program us intended for those back-end engineers who will be implementing and verifying a power efficient design.
DescriptionThe goal of this offering is to supply the learner with the information needed to be self sufficient in the various aspects of designing and implementing a power efficient design. This will be accomplished through a series of lectures describing fundamentals and design considerations for power efficiency, followed by lectures on tool usage, and concluding with labs to use the tools and to reinforce the lectures.
The Power Efficient Design offering starts with an introduction to low power design fundamentals. Next, the student will either go through the Logic Design Track, or the Digital-Implementation track.
The Logic-Design Track: The Cadence low power simulation, logic design, and verification flow will be introduced along with a description of RTL Coding styles that can result in the greatest power savings. You will explore several requirements and validation issues with respect to the library especially for logic design and verification process. One of the most challenging aspects of low power design is accurately predicting what the power consumption will be and deciding on the optimal course of action to reduce it. RTL Compiler can help with this important task. You will discover how to generate several reports in RTL Compiler which will provide you with power consumption estimates that you can use to drive your next steps. Next, you will learn how to communicate your design's low-power features to the simulator and downstream tools with the Common Power Format (CPF) file. You will also learn to collect and evaluate coverage data during verification. You will use RTL Compiler directives and the CPF file to set the power intent and to synthesize your low power design.
The Design-Implementation Track: The Cadence low power implementation, verification and analysis flow will be introduced. You will explore several requirements and validation issues with respect to the library, especially for implementation and verification. You will discover how to generate several reports in RTL Compiler which will provide you with power consumption estimates. Next, you will run synthesis using RTL Compiler, design implementation using SoC Encounter. You will learn the fundamentals of power-grid analysis and run sign-off power grid verification using the VoltageStorm tool. You will also learn advanced techniques that you can use to implement you low power design.
Once you have completed one or both of the tracks, you will continue by learning to use the Encounter Conformal Low Power verification tool. The package will conclude with lectures and discussions about how to project-manage your low power design and how you will analyze and evaluate the best techniques to use for your next low-power design.
Along with projects, group activities, in-class quizzes, assessments and assignments will be used to ensure that critical topics are understood. Books and suggested readings will also be provided to reinforce the material being presented.
Learning ObjectivesIn this program, you will learn to:
- Articulate the principles of power efficient design.
- Analyze the tradeoffs of reducing the power consumption at each stage of the design process: from architecture through implementation.
- Develop the vocabulary and in-depth understanding of power efficient design to better communicate with the various design teams about power efficient design.
- Develop hand-off procedures between design teams to meet well-defined power goals on schedule.
- Use Enterprise® Simulator and Enterprise® Manager to automatically create CPF-derived assertions and coverage of your power control unit.
- Validate the power estimation of the RTL.
- Create and validate the CPF power constraints that you will use to verify, synthesize and simulate your power efficient design.
- Utilize several techniques to synthesize your design to minimize power consumption
- Verify functional correctness of using PSO/MSV/DVFS techniques in the design.
- Optimize your gate-level netlist for power.
- Create and optimize a power plan for you design.
- Create the power constraints and implement your power efficient design from gates to GDSII.
- Extract and run Power Analysis to measure power consumption and IR drop at various stage of the design process.
- Run structural and functional verification on the power-efficient design.
AgendaDay One (Common to Logic Design and Design Implementation Tracks) - Low Power Fundamentals
You will be able to:
- Understand the main concepts behind multi-chip modules.
- Understand the main concepts behind multi-chip modules.
- Define multi-chip module connectivity using spreadsheet based System Architect connectivity tool.
- Transfer a logical design netlist to a physical design netlist.
- Create design hierarchy to reduce the time required to define the logical design.
- Associate discrete components with active components for terminations and decoupling.
Logic Design Track
Day Two - Low power flow, library requirements, power estimation, simulation, and synthesis
You will be able to:
- Summarize the low power flow in the areas of architecture, RTL Synthesis, CPF development, library validation and verification.
- Explore RTL Compiler Power Estimation
- Explore Leakage Power Reduction Techniques
- Discuss Low-Power Challenges in the context of simulation
Day Three and Four - Low power flow, power estimation, simulation, and synthesis You will be able to:
- Articulate Hierarchical CPF support in the context of simulation
- Create and run CPF-Enabled Simulations, low-power debug and Coverage
- Debug power-mode-related failures in an Enterprise Manager environment.
- Analyze and synthesize the design for low-power structures using the Common Power Format (CPF) to represent the power intent for your design.
- Run Synthesis with Low Power directives and libraries to optimize the leakage and dynamic power of a design.
Digital Implementation Track
Days Two, Three and Four - Low Power flow, library requirements, power estimation, low power implementation and low power formal verification.
You will be able to:
- Summarize the low power flow in the areas of implementation, verification and power grid analysis.
- Select and validate your low power library
- Explore RTL Compiler's Power estimation features
- Create and use the Si2 Common Power Format file (both flat and hierarchical) to specify the power intent of your design.
- Set up and run synthesis directives and constraints to reduce dynamic and leakage power
- Implement multi-supply voltage (MSV) regions to reduce power consumption
- Implement a low-power clock tree
- Run concurrent timing, MSV optimization, and multi-Vt (leakage) optimization
- Implement MSV-aware detail routing
- Verify the design implementation by running low-power formal verification
- Analyze data and debug power problems at different stages of the flow.
Day Five and Six: Sign-off Power Grid Analysis and Verification with VoltageStorm.
You will be able to:
- Articulate the principles behind sign-off power-grid analysis and how it fits within the design flow.
- Review what data is required and used during VoltageStorm power-grid analysis
- Run static and dynamic power-consumption analysis using PowerMeter
- Validate power grids and inserted power gates
- Study how to optimize decoupling capacitance and run dcap optimization.
- Run power-up analysis
- Study the common power format and run advanced power rail analysis
Day Seven and Eight: Advanced Low Power techniques
You will be able to:
- Define and use different types of complex power structures from the low power library in your design.
- Explore the tradeoffs of different power shut-off (switching) schemes in implementation.
- Run power domain verification
- Optimize the power switches
- Set up your design for multi-mode multi-corner optimization and analysis
- Place the well tap cells and route power to them for the bias pins.
- Place single and multi-height well separator cells
- Place and route always-on buffers for optimization
- Run buffer-tree synthesis for always-on nets
- Explore power-domain support for adding filler cells
- Explore the decap optimization flow
- Create a CPF for implementing a top-down and bottom-up hierarchical design methodologies.
Final Day (Common to both the Logic Design and Implementation Tracks) - Low Power Structural Verification and Project Planning
You will be able to:
- Run Encounter Conformal Low Power verification to check your design for structural and functional errors and verify your low power design.
- Learn how to plan you next low power design project so that it meets your power goals and schedule.
Offering LengthComplete Track: 13 days
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