|
|
1. INTRODUCTIONThe usage of advanced process nodes and the scale of integration of smaller and faster transistors have resulted in ever-increasing power dissipation. Whether the need to reduce power consumption comes from extending battery life, increasing a chip's reliability by reducing the heat that's produced, or because of environmental concerns, power efficiency is a vital design consideration.
This offering combines tools, methodology, best practices, and design experience to provide a cost-effective and low-risk program enabling teams to bridge knowledge gaps associated with significant technology and team transitions. It replaces the typical training techniques that usually include:
- Learning on-the-fly, or learning from mistakes
- Ad-hoc training from manuals, web help, and so on
- Reduced productivity of experienced staff that will need to spend time mentoring others in power-efficient design
The goal of this offering is to provide the learner with the information needed to be self-sufficient in the various aspects of designing and implementing a power-efficient design. This will be accomplished through a series of lectures describing fundamentals and design considerations for power efficiency, followed by lectures on tool usage, and concluding with labs to use the tools and to reinforce the lectures.
The Cadence® Power-Efficient Design series starts with an introduction to low-power design fundamentals. Next, the student will either go through the Logic Design Track or the Digital Implementation Track.
2. AUDIENCEThe Power-Efficient Design curriculum is offered in two tracks:
- The Logic Design Track: This track is intended for those front-end engineers who will be architecting, simulating, synthesizing, and verifying a power-efficient design
- The Digital Implementation Track: This track is intended for those back-end engineers who will be implementing and verifying a power-efficient design
3. COURSE SERIES ABSTRACT
3.1 THE LOGIC DESIGN TRACK The Cadence low-power simulation, logic design, and verification flow will be introduced along with a description of RTL coding styles that can result in the greatest power savings. You will explore several requirements and validation issues with respect to the library especially for logic design and verification process. One of the most challenging aspects of low-power design is accurately predicting what the power consumption will be and deciding on the optimal course of action to reduce it. Encounter® RTL Compiler can help with this important task. You will discover how to generate several reports in RTL Compiler that will provide you with power consumption estimates that you can use to drive your next steps. Next, you will learn how to communicate your design's low-power features to the simulator and downstream tools with the Common Power Format (CPF) file. You will also learn to collect and evaluate coverage data during verification. You will use RTL Compiler directives and the CPF file to set the power intent and to synthesize your low-power design.
3.2 THE DESIGN IMPLEMENTATION TRACKThe Cadence low-power implementation, verification, and analysis flow will be introduced. You will explore several requirements and validation issues with respect to the library, especially for implementation and verification. You will discover how to generate several reports in Encounter RTL Compiler that will provide you with power consumption estimates. Next, you will run synthesis using RTL Compiler and design implementation using the SoC Encounter™ RTL-to-GDSII System. You will learn the fundamentals of power-grid analysis and run signoff power grid verification using the VoltageStorm® Power Verification tool. You will also learn advanced techniques that you can use to implement your low-power design.
Once you have completed one or both of the tracks, you will continue by learning to use the Encounter Conformal® Low Power verification tool. The series will conclude with lectures and discussions about how to project-manage your low-power design and how you will analyze and evaluate the best techniques to use for your next low-power design. Along with projects, group activities, in-class quizzes, assessments, and assignments will be used to ensure that critical topics are understood. Books and suggested readings will also be provided to reinforce the material being presented.
4. POWER-EFFICIENT DESIGN CURRICULUM OBJECTIVES
- Articulate the principles of power-efficient design
- Analyze the tradeoffs of reducing the power consumption at each stage of the design process: from architecture through implementation
- Develop the vocabulary and in-depth understanding of power-efficient design to better communicate with the various design teams about power-efficient design
- Develop hand-off procedures between design teams to meet well-defined power goals on schedule
- Use Incisive® Enterprise Simulator and Incisive Enterprise Manager to automatically create CPF-derived assertions and coverage of your power control unit
- Validate the power estimation of the RTL
- Create and validate the CPF power constraints that you will use to verify, synthesize, and simulate your power-efficient design
- Utilize several techniques to synthesize your design to minimize power consumption
- Verify functional correctness of using PSO/MSV/DVFS techniques in the design
- Optimize your gate-level netlist for power
- Create and optimize a power plan for you design
- Create the power constraints and implement your power-efficient design from gates to GDSII
- Extract and run power analysis to measure power consumption and IR drop at various stage of the design process
- Run structural and functional verification on the power-efficient design
Associated Tool Training
- Encounter RTL Compiler
- SoC Encounter XL
- Encounter Low-Power Verification
- Encounter Power System XL
5. POWER-EFFICIENT DESIGN CURRICULUM AGENDA This curriculum offering is designed as a multi-course approach to providing Power-Efficient Design techniques and expertise. The individual courses included in this series offering are:
- Low-Power Fundamentals
- Low-Power Flow, Power Estimation, Simulation, and Synthesis
- Low-Power Flow, Physical Implementation, and Formal Verification
- Signoff Power Grid Analysis with Encounter Power System
- Advanced Low-Power Implementation Techniques
- Low-Power Structural Verification and Project Planning
Each of the above courses is described in the following sections.
5.1 LOW-POWER FUNDAMENTALS V1.0
Course Name: Design Foundations: Low-Power Fundamentals v1.0
Course Duration: 1 day (8 hours)
Course Number: ES_82195_1.0
Course Agenda:
- Explore why power is a critical design criterion
- Evaluate how process migration is adversely affecting power
- Explore design techniques to reduce power
- Identify why verification is a key part of the design process
- Articulate how low-power techniques have an impact on timing and area
5.2 LOW-POWER FLOW, POWER ESTIMATION, SIMULATION, AND SYNTHESIS
Course Name: Design Foundations: Low-Power Flow, Power Estimation, Simulation, and Synthesis v1.0
Course Duration: 3 days (24 hours)
Course Number: ES_82196_1.0
Course Agenda:
Day 1:
- Summarize the low-power flow in the areas of architecture, RTL synthesis, CPF development, library validation, and verification
- Explore Encounter RTL Compiler power estimation
- Explore leakage power reduction techniques
- Discuss low-power challenges in the context of simulation
Days 2 and 3:
- Articulate hierarchical CPF support in the context of simulation
- Create and run CPF-enabled simulations, low-power debug and coverage
- Debug power-mode–related failures in an Incisive Enterprise Manager environment
- Analyze and synthesize the design for low-power structures using the Common Power Format (CPF) to represent the power intent for your design
- Run synthesis with low-power directives and libraries to optimize the leakage and dynamic power of a design
5.3 LOW-POWER FLOW, PHYSICAL IMPLEMENTATION, AND FORMAL VERIFICATION
Course Name: Design Foundations: Low-Power Flow, Physical Implementation, and Formal Verification v1.0
Course Duration: 3 days (24 hours)
Course Number: ES_82197_1.0
Course Agenda:
- Summarize the low power flow in the areas of implementation, verification and power grid analysis.
- Select and validate your low power library
- Explore RTL Compiler’s Power estimation features
- Create and use the Si2 Common Power Format file (both flat and hierarchical) to specify the power intent of your design.
- Set up and run synthesis directives and constraints to reduce dynamic and leakage power
- Implement multi-supply voltage (MSV) regions to reduce power consumption
- Implement a low-power clock tree
- Run concurrent timing, MSV optimization, and multi-Vt (leakage) optimization
- Implement MSV-aware detail routing
- Verify the design implementation by running low-power formal verification
- Analyze data and debug power problems at different stages of the flow.
5.4 SIGNOFF POWER GRID ANALYSIS WITH ENCOUNTER POWER SYSTEM
Course Name: Design Foundations: Signoff Power Grid Analysis and Verification with Encounter Power System v8.1
Course Duration: 2 days (16 hours)
Course Number: ES_82169_8.1
Course Overview:This is an Engineer Explorer course for designers who need a comprehensive and detailed understanding of power rail analysis for advanced processes. In this two-day course, you explore the need for power-rail analysis and use the Encounter Power System power consumption and power rail verification software to run several types of power-consumption and power-rail analyses. In the first day of the course, you run early rail analysis using SoC Encounter XL technology, and basic rail and IR drop analysis using Encounter Power System. You create power-grid view libraries. You also run static and dynamic power-consumption analyses. In the second day of the course, you study more advanced power rail analysis, decapacitance optimization, the Common Power Format (CPF), and power-up analysis.
Course Agenda:
Day 1:
- Perform early rail analysis
- Articulate aspects of the Encounter Power System
- Build libraries
- Perform static and dynamic power consumption analysis
Day 2:
- Perform power rail analysis
- Understand the Common Power Format
- Perform power-up analysis
5.5 ADVANCED LOW-POWER IMPLEMENTATION TECHNIQUES
Course Name: Design Foundations: Advanced Low-Power Implementation Techniques v1.0
Course Duration: 2 days (16 hours)
Course Number: ES_82199_1.0
Course Agenda:
- Define and use different types of complex power structures from the low-power library in your design
- Explore the tradeoffs of different power shut-off (switching) schemes in implementation
- Run power domain verification
- Optimize the power switches
- Set up your design for multi-mode/multi-corner optimization and analysis
- Place the well tap cells and route power to them for the bias pins
- Place single- and multi-height well separator cells
- Place and route always-on buffers for optimization
- Run buffer-tree synthesis for always-on nets
- Explore power-domain support for adding filler cells
- Explore the decap optimization flow
- Create a CPF for implementing a top-down and bottom-up hierarchical design methodologies
5.6 LOW-POWER STRUCTURAL VERIFICATION AND PROJECT PLANNING
Course Name: Design Foundations: Low-Power Structural Verification and Project Planning v1.0
Course Duration: 1 day (8 hours)
Course Number: ES_84478_1.0
Course Agenda:
- Run Encounter Conformal Low Power verification to check your design for structural and functional errors and verify your low-power design
- Learn how to plan you next low-power design project so that it meets your power goals and schedule
|
|
|
|