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Finding Design Bugs Faster Using Violations Assertion Based Verification 

I want to assert system behavior and have the simulator report violations as they occur rather than after the fact.

You can make assertions about system behavior and embed them in your source code and/or place them in an auxiliary file. These assertions are much more concise than lengthy testbench code you might otherwise write to monitor system behavior. The Incisive® Design Team Simulator and Incisive® Enterprise Specman Simulator can immediately report system behavior that violates your assertions, saving you untold subsequent debug effort. With the Incisive® Formal Verifier, you don't even need to wait for a testbench, letting you verify the system as you develop and integrate it. You can write assertions in the language-neutral Property Specification Language (PSL), or as SystemVerilog Assertions (SVA). You can instantiate predefined Accellera Open Verification Library (OVL) assertion components, and components of the more populated Incisive® Assertion Library.
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