This is an Engineer Explorer series course. The Engineer Explorer courses explore advanced topics.
This course gives you an in-depth introduction to the main design convenience and synthesis features which SystemVerilog adds to the Verilog? hardware description language (HDL). The course discusses the benefits of the new features and demonstrates how more efficiently and effectively you can design when using the new SystemVerilog constructs.
After completing this course you will be able to:
- Understand the new SystemVerilog design features and demonstrate their use to improve design efficiency.
- Exploit the full range of SystemVerilog improvements for RTL design, including new data types, operators, and statements, changes to Verilog language rules, fixes for case synthesis issues, and powerful new connectivity features.
Software Used in This Course
- Incisive Enterprise Simulator L
Modules in this Online Course
This course consists of one module covering:
- SystemVerilog overview
- New standard data types and literals
- Procedures and procedural statement enhancements
- User-defined data types, such as enumerations, packed arrays, and structures
- Hierarchy and connectivity changes
- Sharing declarations with packages
- Task and function improvements
You must have:
- Ability to navigate a filesystem and use a text editor
- Basic understanding of digital hardware design and verification
- Working knowledge of the Verilog HDL
System Requirements for Online Courses
- Cadence software installed and licensed
- SystemVerilog for Verification
- Verilog Language for Design
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