This is an Engineer Explorer series course. The Engineer Explorer courses explore advanced topics.
This course gives you an in-depth introduction to the main design, convenience and synthesis features which SystemVerilog adds to the Verilog® hardware description language (HDL). The course discusses the benefits of the new features and demonstrates how you can design more efficiently and effectively when using the new SystemVerilog constructs.
After completing this course you will be able to:
- Understand the new SystemVerilog design features and demonstrate their use to improve design efficiency.
- Exploit the full range of SystemVerilog improvements for RTL design, including new data types, literals, procedural blocks, statements, and operators; relaxation of Verilog language rules; fixes for synthesis issues; enhancements to tasks and functions; new hierarchy and connectivity features, and interfaces.
Software Used in This Course
- Incisive Enterprise Simulator L
Modules in this Online Course
- SystemVerilog Overview
- Standard Data Types and Literals
- Procedures and Procedural Statements
- User-Defined Data Types and Structures
- Hierarchy and Connectivity
- Tasks and Functions
- Conclusions and Next Steps
You must have:
- Ability to navigate a filesystem and use a text editor
- Basic understanding of digital hardware design and verification
- Working knowledge of the Verilog HDL
System Requirements for Online Courses
- Cadence software as listed above installed and licensed
Click here to view course learning maps, and here for complete course catalogs.