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NA Training Course Detail 

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Delivery MethodVersionDatesLocationsLengthCost 
Online14.1Available 24 hours, 7 days a week.Online  1575.00Register »
 More Online
Instructor Led14.220 Jul 2015 - 22 Jul 2015Cadence San Jose > ES Training Room SJ1124  Hrs2100.00Register »
Instructor Led14.227 Jul 2015 - 29 Jul 2015Cadence Austin > ES Training Room A124  Hrs2100.00Register »
Instructor Led14.1Scheduled upon demand 24  Hrs2100.00Express Interest »

Course ID:  ES_82160_14.2

Course Description

In this course, you explore high-level design planning and implementation by using the Encounter® Digital Implementation software. You learn several techniques for floorplanning and placement while implementing timing closure strategies. You run the detail router to route a design, fix routing violations, and use timing and signal integrity options. You will explore challenges and solutions when using double-patterning lithography in design implementation.

Other topics in this course include extracting parasitics, creating clock trees (CCOpt), running delay calculation, and using database access commands. You also explore wire editing, metal fill, ECO, and physical verification.

Learning Objectives

After completing this course, you will be able to:

  • Floorplan a design
  • Place blocks and standard cells
  • Run scan optimization
  • Run Trial Route
  • Route the power
  • Estimate parasitics and run timing analysis
  • Analyze routing congestion
  • Create clock trees
  • Modify net attributes
  • Edit wires manually
  • Route with signal integrity options
  • Extract RC data
  • Optimize and close timing
  • Fix routing violations
  • Route in ECO mode
  • Address double-patterning design challenges
  • Run database access commands
  • Run foundation flow scripts

Software Used in This Course

  • Encounter Digital Implementation System XL

Software Release(s)

  • EDI142

Course Agenda

Note that this course can be tailored to better meet your needscontact the Cadence training staff for specifics.

Day 1

  • Floorplanning the design
  • Planning power
  • Routing power
  • Placing cells and blocks
  • Optimizing and reordering scan chains
  • Analyzing route feasibility using Trial Route

Day 2

  • Extracting parasitics and analyzing timing
  • Running optimization and closing timing
  • Implementing the clock tree (CCOpt)
  • Double-patterning lithography challenges (20nm and below)

Day 3

  • Selecting routing attributes and options
  • Performing wire editing and metal fill
  • Running signal integrity
  • Running database access commands
  • Implementing an engineering change order
  • Writing out a design
  • Creating and running Foundation Flow scripts

Audience

  • CAD Engineers
  • Chip Designers
  • Physical Layout Designers

Prerequisites

You must have experience with or knowledge of:

  • Design methodology
  • Place and Route

Related Courses

Click here to view course learning maps, and here for complete course catalogs.

Special Note

This course does not include RTL synthesis. For detailed knowledge of running RTL synthesis, take the Encounter® RTL Compiler course.