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NA Training Course Detail 

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Delivery MethodVersionDatesLocationsLengthCost 
Online14.1Available 24 hours, 7 days a week.Online  1575.00Register »
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Instructor Led14.226 Jan 2015 - 28 Jan 2015Cadence San Jose > ES Training Room SJ1124  Hrs2100.00Register »
Instructor Led14.1Scheduled upon demand 24  Hrs2100.00Express Interest »
Instructor Led13.2Scheduled upon demand 24  Hrs2100.00Express Interest »
Instructor Led13.1Scheduled upon demand 24  Hrs2100.00Express Interest »
Instructor Led11.1Scheduled upon demand 24  Hrs2100.00Express Interest »
Virtual Instructor13.2Scheduled upon demand 20  Hrs2100.00Express Interest »
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Course ID:  ES_82160_10.1

Course Description

In this course, you explore high-level design planning and implementation by using the Encounter® Digital Implementation software. You learn several techniques for floorplanning and placement while implementing timing closure strategies. You run the detail router to route a design, fix routing violations, and use timing and signal integrity options.

Other topics in this course include extracting parasitics, creating clock trees, running delay calculation, and using database access commands. You also explore wire editing, metal fill, ECO, and physical verification.

Learning Objectives

After completing this course, you will be able to:

  • Floorplan a design
  • Place blocks and standard cells
  • Run scan optimization
  • Run Trial Route and route the power
  • Estimate parasitics and generate timing information
  • Analyze routing congestion
  • Create clock trees
  • Run power analysis
  • Modify net attributes
  • Edit wires manually
  • Route with signal integrity options
  • Extract RC data
  • Optimize and close timing
  • Fix routing violations
  • Route in ECO mode
  • Run database access commands
  • Run foundation scripts

Software Used in This Course

  • Encounter Digital Implementation System XL

Software Release(s)

  • EDI101

Course Agenda

Note that this course can be tailored to better meet your needscontact the Cadence training staff for specifics.

Day 1

  • Floorplanning the design
  • Planning power
  • Placing cells and blocks
  • Optimizing and reordering scan chains
  • Analyzing route feasibility using Trial Route

Day 2

  • Extracting parasitics and analyzing timing
  • Running optimization and closing timing
  • Implementing the clock tree
  • Routing power
  • Analyzing power

Day 3

  • Selecting routing attributes and options
  • Performing wire editing and metal fill
  • Running signal integrity
  • Running database access commands
  • Implementing an engineering change order
  • Writing out a design
  • Creating and running Foundation Flow scripts

Audience

  • CAD Engineers
  • Chip Designers
  • Physical Layout Designers

Prerequisites

You must have experience with or knowledge of:

  • Design methodology
  • Place and Route

Related Courses

  • Encounter RTL Compiler
  • Floorplanning, Physical Synthesis, Place and Route (Hierarchical)
  • Logic Equivalence Checking with Encounter Conformal EC
  • Low Power Implementation

Click here to view course learning maps, and here for complete course catalogs.

Special Note

This course does not include RTL synthesis. For detailed knowledge of running RTL synthesis, take the Encounter® RTL Compiler course.