Course Description
In this course, you learn to verify low-power designs using Encounter® Conformal® Low Power. In the labs, you debug practical examples of common power format (CPF) violations, functional and structural violations, and nonequivalences.
Learning Objectives
After completing this course, you will be able to:
- Identify Encounter® Conformal® Low Power features
- Run the software for low power verification
- Debug CPF Violations
- Debug Functional Violations
- Analyze power domains using structural checks
- Analyze and debug the low power nonequivalences
- Verify RTL, synthesized, and post-routed netlists
Software Used in This Course
- Encounter Conformal Low Power GXL
Software Release(s)
Course Agenda
Note that this course can be tailored to better meet your needs – contact the Cadence training staff for specifics.
Day 1
- Overview
- Library Preparation
- Logical Verification
- Physical Verification
- Using CLP Successfully
- Using Power Intent Architect
- Handling IO Pads
- Liberty Support
Audience
-
ASIC Designers
- Design Engineers
- Digital IC Designers
- FPGA Designers
- Hardware Engineers
- Logic Designers
- Verification Engineers
Prerequisites
You must have experience with or have knowledge of the following:
- Design methodology
- Logic Design
- HDL
- Encounter Conformal XL
Or you must have completed the following courses:
- Logic Equivalence Checking with Encounter Conformal EC
Related Courses
- Advanced Logic Equivalence Checking with Encounter Conformal EC
- Logic Equivalence Checking with Encounter Conformal EC
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