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NA Training Course Detail 

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Delivery MethodVersionDatesLocationsLengthCost 
Online Subscription Available 24 hours, 7 days a week.Online2912.00Register »
Online15.2Available 24 hours, 7 days a week.Online  546.00Register »
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Instructor Led15.2Scheduled upon demand 16  Hrs1456.00Express Interest »

Course ID:  ES_82123_15.2

Course Description


In this class you learn to use the Conformal Equivalence Checker to perform functional verification. You learn the basic flow of equivalence checking and also learn to run hierarchical comparison of designs. The lab exercises follow major topics and are designed to be directly applicable in design and design verification. Upon completion of this course, you will be able to set up and verify your designs, analyze the results, and debug failing results.

Learning Objectives

After completing this course, you will be able to:

  • Use Encounter Conformal logic equivalence checking for flat and hierarchical design comparison
  • Read libraries and designs
  • Apply design constraints and modeling directives
  • Apply the mapping process and debug unmapped key points
  • Apply the compare process and debug non-equivalent points
  • Run and debug a hierarchical design comparison
  • Run the debugging of the setup of a design
  • Run the debugging of the mapping of a design
  • Analyze and fix the nonequivalences of a design
  • Analyze and fix the aborts in a design

Software Used in This Course

  • Encounter Conformal XL

Software Release(s)

  • CONFRML152

Course Agenda

Note that this course can be tailored to better meet your needscontact the Cadence training staff for specifics.

Day 1

  • Introduction to the Encounter Conformal product family
  • Introduction to logic equivalence checking
  • LEC flow - Setup mode
  • LEC flow - LEC mode

Day 2

  • Hierarchical comparison of designs
  • Debugging Setup Issues
  • Debugging Mapping Issues
  • Debugging Nonequivalences
  • Debugging Aborts


  • ASIC Designers
  • Logic Designers
  • Verification Engineers


You must have experience with or knowledge of:

  • HDL
  • Logic Design

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